Vector clock

Abstract: A probabilistic method is proposed for reading remote clocks in distributed systems subject to unbounded random communication delays. The method can achieve clock synchronization precisions superior to those attainable by previously published clock synchronization algorithms. Its use is illustrated by presenting a time service which maintains externally (and hence, internally) synchronized clocks in the presence of process, communication and clock failures.

Abstract: Algorithms are described for maintaining clock synchrony in a distributed multiprocess system where each process has its own clock. These algorithms work in the presence of arbitrary clock or process failures, including “two-faced clocks” that present different values to different processes. Two of the algorithms require that fewer than one-third of the processes be faulty. A third algorithm works if fewer than half the processes are faulty, but requires digital signatures.

Abstract: A gaming machine uses a time-based method for generating game results having nonuniform probability. The gaming machine employs an addressable memory in cooperation with a counter and a clock. The clock generates a very fast series of pulses, and includes a digital-to-analog converter. The counter holds a number representing one of the possible reel stop positions and counts the clock's pulses, so that with each pulse, the value of the counter advances by one. To vary the odds that a particular reel stop position will be selected, the clock's pulses do not come at even intervals. Rather, the clock is responsive to a digital input signal to control how long it will allow a particular number to remain in the counter before the next clock pulse. The binary numbers which are used to control the clock are stored in memory. The memory accepts as input the current value of the counter. Thus, when the counter is incremented, the memory provides the binary number associated with the new counter value. By selecting appropriate binary numbers for each possible counter value, the relative amounts of time which the counter holds each value (and, therefore, the probability of selection) can be varied.

Abstract: A circuit for detecting timing errors between a binary signal and a local clock pulse generator is described. Three binary samples are compared and logical control signals for the clock are derived.