TL;DR: Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits as discussed by the authors, and the impact of technology trends on single event susceptibility and future areas of concern are explored.
Abstract: Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.
TL;DR: In this article, the authors review various single event effects (SEE) testing and rate prediction methodologies and recommend standard approaches for directionization-induced SEU rate prediction, based partially on a different way of viewing the results of SEU cross-section measurements.
Abstract: The authors review various single event effects (SEE) testing and rate prediction methodologies and recommend standard approaches. This discussion is limited to single event upset (SEU) rate prediction for direct-ionization-induced effects. The standard approach being recommended is based partially on a different way of viewing the results of SEU cross-section measurements. The measurements are not measuring a distribution of cross-sections. They are measuring a distribution of device sensitivities, due to differences of sensitive region critical charges and to differences of charge collection. The linear energy transfer (LET), at which 50% of the cell population upsets, corresponds to the charge deposition necessary to upset the median cell in the circuit array. The threshold LET corresponds to the most sensitive region being hit in its most sensitive location, and does not represent the entire array. The shape of the cross-section curve is described by an integral Weibull distribution. The upset rate for a device should then be calculated using the differential rate of each sensitive region, combined with an integral weighting given by the Weibull distribution that describes the measured cross-section curve. >
TL;DR: In this article, error detection and correction circuitry for all avionics designs containing large amounts of semiconductor memory was suggested for all aircraft designs, including SRAMs and NVRAMs, and it was shown that typical nonradiation-hardened 64 K and 256 K static random access memories (SRAMs) experienced a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere.
Abstract: Data from military/experimental flights and laboratory testing indicate that typical non-radiation-hardened 64 K and 256 K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere. It is suggested that error detection and correction circuitry be considered for all avionics designs containing large amounts of semiconductor memory. >
TL;DR: In this article, the effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations, and the results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.
Abstract: The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.
TL;DR: In this article, a method for producing homogeneous wrought microstructure during equal channel angular extrusion of difficult-to-work high temperature alloys that exhibit a high degree of flow softening at hot working temperatures is described.