Transputer

Abstract: The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

Abstract: The transputer is a programmable VLSI component with communication links for point-to-point connection to other transputers. Occam (*) is a language that enables a multi-transputer system to be described as a collection of processes that ogerate concurrently and communicate using message passing via named channels. The INMOS transputer architecture is standardized at the level off the definition of occam (rather than at the level of the definition of an instruction set). The implementation of the first commercially available transputers is illustrated by describing the implementation of occam. The paper concludes with outline examples of some applications. 1 Introduction The transp~ater architecture has been developed to fulfil four main objectives: To create a commercial product range that sets new standards in ease of programming and ease of engineering. To provide the maximum performance to the user. To exploit future developments in VLSI technology within a compatible family. To create a programmable component that can be used to build systems with large numbers of concurrent computing elements. VLSI currently permits 5-10 MIP processors to be manufactured in volume for low prices. There is therefore no economic barrier to the construction of very powerful computer systems containing many processing elements, The challenge is a technical one: how to engineer a system with, say, 1000 processors so as to make the inherent concurrency usable, and how to support the design of applications to take advantage of this amount of concurrency. (*) oceam is a trade mark of the INMOS Group of Companies In the transputer architecture, the exploitation of a high degree of concurrency is made possible through a decentralized model of computation, in which local computation takes place on local data, and concurrent processes communicate by passing messages on point to point channels. The localized communications architecture also has substantial engineering advantages, described below. An important design objective of oecam and the transputer was to provide the same concurrent programming techniques both for a single transputer and for a network of transputers. Consequently, the features of occam were chosen to ensure an efficient distributed implementation on transputer systems. The concurrent processing mechanisms within the transputer were then designed to match. The result is that a program ultimately intended for a network of transputers can be compiled and executed efficiently by a single computer used for program development. Once the logical behaviour of the program has been verified, the program may be configured for …

Abstract: An overview of research of high-speed transport components is given. High-speed protocols as well as high-speed implementations are considered. The use of parallelism to increase the performance of communication nodes is considered. A parallel implementation of Open Systems Interconnection (OSI) protocols on transputer networks based on the parallel concepts discussed is described. Selected performance values of the implementations are presented. The outlook on the design of high-speed transport components for future communication systems is examined. >