Topic
Three-state bus
About: Three-state bus is a research topic. Over the lifetime, 4 publications have been published within this topic receiving 32 citations.
Papers
Patent•
8 Jan 1993TL;DR: In this paper, a structure and method for evaluating control and data input signals to a three-state bus to determine whether the control input signals result in either a contention on the three state bus or floating of the 3 state bus is disclosed.
Abstract: A structure and method, useful in a test pattern generation system, for evaluating control and data input signals to a three state bus to determine whether the control input signals result in either a contention on the three state bus or floating of the three state bus is disclosed. Two parallel logic networks are used. A first logic network receives both the control input signals and data input signals and in turn generates an output signal that is the output signal of the three state bus. The second logic network receives only the control input signals and in turn generates an output signal having a first predetermined value when the bus output signal is valid and a second predetermined value when either a contention exists on the three state bus or the three state bus is floating. Selection of test vectors that produce only control signals that in turn produce an output signal from the second logic network having the first predetermined value results in selection of only valid test vectors.
15 citations
Patent•
11 Oct 1977TL;DR: In this article, the authors proposed a three-state bus driver with insulated gate field effect transistors for protection against short circuiting of the output bus, where the ON transistor senses the short circuit condition of two push-pull output transistors and feeds back a signal to the input circuit of ON transistor which reduces the input drive to that transistor and limits the output current through that transistor to a safe value.
Abstract: A protective circuit arrangement for three state bus drivers, incorporating insulated gate field effect transistors, affords protection against short circuiting of the output bus. The protective circuit senses the short circuit condition at the output bus of two push-pull output transistors and feeds back a signal to the input circuit of the ON transistor which reduces the input drive to that transistor and limits the output current through that transistor to a safe value.
11 citations
Patent•
3 May 1979TL;DR: In this paper, an apparatus and method for providing an accurate data group to the instruction buffer of a data pro-cessing system is described. But the data group is simultaneously applied to the Instruction buffer and to the error correcting apparatus.
Abstract: This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data pro-cessing system. The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting ap-paratus, the operation in progress is aborted if an error has been detected, and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted. Two, three state busses are employed. The first three state bus is used to transmit memory data to the error detection and correction (EDAC) circuitry, to transmit corrected data from the (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state bus transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from data output circuits to the instruction buffer.
5 citations
Patent•
5 May 2000
TL;DR: In this article, a programmable synchronous three-state control circuit is connected to the set of three state driver columns, which responds to a control signal and select signals to produce a threestate output enable signal, which is applied to a selected threestate driver column of a set of 3-state driver columns so as to control data signals on the data bus.
Abstract: A signal control circuit includes a set of signal lines that form a data bus. A set of three-state driver columns is connected to the data bus; each three-state driver column is connected to each signal line of the set of signal lines. A programmable synchronous three-state control circuit is connected to the set of three-state driver columns. The programmable synchronous three-state control circuit responds to a control signal and select signals to produce a three-state output enable signal which is applied to a selected three-state driver column of the set of three-state driver columns so as to control data signals on the data bus.
1 citations
Performance Metrics
| Year | Papers |
|---|---|
| 2000 | 1 |
| 1993 | 1 |
| 1979 | 1 |
| 1977 | 1 |