Topic
Technology CAD
About: Technology CAD is a research topic. Over the lifetime, 781 publications have been published within this topic receiving 5343 citations. The topic is also known as: Technology Computer Aided Design & TCAD.
Papers published on a yearly basis
Papers
TL;DR: In this paper, the authors identify the root cause for the increase of the remnant polarization during the wake-up phase and subsequent polarization degradation with further cycling of a hafnium oxide-based ferroelectric random access memory (FeRAM).
Abstract: Novel hafnium oxide (HfO2)-based ferroelectrics reveal full scalability and complementary metal oxide semiconductor integratability compared to perovskite-based ferroelectrics that are currently used in nonvolatile ferroelectric random access memories (FeRAMs). Within the lifetime of the device, two main regimes of wake-up and fatigue can be identified. Up to now, the mechanisms behind these two device stages have not been revealed. Thus, the main scope of this study is an identification of the root cause for the increase of the remnant polarization during the wake-up phase and subsequent polarization degradation with further cycling. Combining the comprehensive ferroelectric switching current experiments, Preisach density analysis, and transmission electron microscopy (TEM) study with compact and Technology Computer Aided Design (TCAD) modeling, it has been found out that during the wake-up of the device no new defects are generated but the existing defects redistribute within the device. Furthermore, vacancy diffusion has been identified as the main cause for the phase transformation and consequent increase of the remnant polarization. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device together with modeling of the degradation results in an understanding of the main mechanisms behind the evolution of the ferroelectric response.
757 citations
26 Oct 2006
TL;DR: In this article, the authors discuss device physics, modeling and design issues of nanoscale transistors at the quantum level, and explore device design issues near the ultimate scaling limit with the help of the developed tools.
Abstract: This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2) development of a new TCAD (technology computer aided design) tool for quantum level device simulation, 3) examination and assessment of new features of carrier transport in nano-scale transistors, and 4) exploration of device design issues near the ultimate scaling limit with the help of the developed tools. We concentrate on the technical issues by investigating a double-gate structure, which has been widely accepted as the ideal device structure for ultimate CMOS scaling. We focus on quantum effects and non-equilibrium, near-ballistic transport in extremely scaled transistors (in contrast to quasi-equilibrium, scattering-dominant transport in long channel devices), where a non-equilibrium Green’s function formalism (NEGF) has been used to deal with the quantum transport problem.
113 citations
TL;DR: The impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors.
Abstract: Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant (RD) fluctuations are significant in current technology nodes. In this paper, the impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors. Line-edge-roughness contributions from the fin, top-, and side wall-gates of n- and p-channel FinFETs are compared by means of 2-D and 3-D technology computer-aided design (TCAD) simulations, performed with a quantum-corrected hydrodynamic model on large statistical ensembles. Correlations between geometrical roughness and resulting electrical parameters are analyzed to provide further insight into the impact of the LER. A noise analysis approach is adopted to evaluate the impact of RD fluctuations throughout the impurity concentration ranges of interest, providing a direct comparison with the line-edge-roughness contributions. The impact of the extension doping profile specifications on the LER- and RD-induced mismatch is investigated, highlighting the potential drawbacks of junction engineering.
108 citations
TL;DR: The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact onThe performance.
Abstract: Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1–xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essent...
99 citations
1 Mar 2001
TL;DR: Limits to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation are explored.
Abstract: As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation.
79 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 4 |
| 2024 | 3 |
| 2023 | 19 |
| 2022 | 22 |
| 2021 | 33 |
| 2020 | 31 |