Table sharing

Abstract: The present disclosure involves systems, software, and computer implemented methods for deploying changes in a multi-tenancy database system One example method includes upgrading at least one tenant database container in a database system Table structure differences and table sharing type differences are determined by comparing tables in a current-version shared container to tables in a next-version shared container A current key pattern configuration in the current-version shared container is compared to an updated key pattern configuration in the next-version shared container to identify key pattern configuration differences Each table in the at least one tenant database container is upgraded based on the table structure differences, the table sharing type differences, and the key pattern configuration differences

Abstract: In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

Abstract: In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle The division instruction among all of the instructions needs more cycles than the rest, eg, addition and multiplication It then, makes division instruction an important CPI (cycles per instruction) figure for modern microprocessors In this paper, a radix 16/8/4/2 divider is proposed which uses a variety of techniques, including operand scaling, table partitioning, and table folding, to increase performance without the cost of increasing complexity

Abstract: In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. This makes the division instruction an important cycles-per-instruction figure for modern microprocessors. In this paper, a radix-16/8/4/2 divisor is proposed, which uses a variety of techniques, including operand scaling, table partitioning, and, particularly, table sharing, to increase performance without the cost of increasing complexity. A physical chip using the proposed method is implemented by 0.35-/spl mu/m single poly four metal (1P4M) CMOS technology. The testing measurement shows that the chip can execute signed 64-b/32-b integer division between 3-13 cycles with a 80-MHz operating clock.