TL;DR: In this article, the payload control information between the first IC and the second IC utilizing a number of data transmission lines was transferred by using a one-bit control signal to identify when payload control is present on all of the data transmission line.
Abstract: An apparatus including a first integrated circuit (IC) (202), a second IC (204), and an interface coupling the first IC to the second IC (200). The interface transfers payload control information between the first IC and the second IC utilizing a number of data transmission lines. On the clock cycle transition following the transfer of payload control information, the interface transfers packetized data between the first IC and the second IC at a data rate of at least approximately 20Gbps utilizing the same transmission lines. A one-bit control signal is used by the interface to identify when payload control information is present on all of the data transmission lines.
TL;DR: An embodiment of a multi-service mapper framer device and methods for operating same are described in this article, which may support the interconnection of synchronous optical networks using the SONET and SDH standards to Ethernet packet networks, and may be capable of mapping up to 2.5 gigabits per second of traffic from a variety of client-side interfaces including time division multiplex T1/E1 and T3/E3 data interfaces, a System Packet Interface, and Ethernet packet data interfaces.
Abstract: An embodiment of a multi-service mapper framer device and methods for operating same are described. This device may support the interconnection of synchronous optical networks using the SONET and SDH standards to Ethernet packet networks, and may be capable of mapping up to 2.5 gigabits per second of traffic from a variety of client-side interfaces including time division multiplex T1/E1 and T3/E3 data interfaces, a System Packet Interface, and Ethernet packet data interfaces. The device may support a trunk-side connection using a T3/E3 data interface, and the ANSI T1X1.5 Generic Framing Procedure and ITU X.86 Ethernet-over-SONET Recommendation may also be supported. Functionality to enable Virtual Concatenation with Link Capacity Adjustment Scheme may be included.
TL;DR: In this paper, a method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.
Abstract: A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.
TL;DR: In this article, a bridging device for implementing the interface bridge between InfiniBand (IB) and system packet interface (SPI) is presented, which is composed of SPI-4 interface logic, IB interfaces logic, processor interface, transmitting channel buffer, transmitting status unit, transmitting-scheduling status unit and transmitting data channel logic.
Abstract: A device for implementing the interface bridge between InfiniBand (IB) and system packet interface (SPI) is composed of SPI-4 interface logic, IB interface logic, processor interface, transmitting channel buffer, transmitting status unit, IB transmitting-scheduling status unit, transmitting data channel logic, transmitting IB head static memory, receiving channel buffer, receiving credit logic, receiving status unit and receiving data channel logic. Its bridging method includes converting SPI datagram to internal datagram, encapsulating, encoding and transmitting it to IB, or decoding the IB datagram, detaching encapsulation, converting it to SPI datagram, and transmitting it to SPI.