Abstract: This paper is devoted to the problem of synchronization of dynamical systems in chaotic oscillations regimes. The authors attempt to use the ideas of synchronization and its mechanisms on a certain class of chaotic oscillations. These are chaotic oscillations for which one can pick out basic frequencies in their power spectra. The physical and computer experiments were carried out for the system of two coupled auto-oscillators. The experimental installation permitted one to realize both unidirectional coupling (external synchronization) and symmetrical coupling (mutual synchronization). An auto-oscillator with an inertial nonlinearity was chosen as a partial subsystem. It possesses a chaotic attractor of spiral type in its phase space. It is known that such chaotic oscillations have a distinguished peak in the power spectrum at the frequency f0 (basic frequency). In the experiments, one could make the basic frequencies of partial oscillators equal or different. The bifurcation diagrams on the plane of con...

Abstract: A digital switching network for providing simultaneous connections among user processors of processor-based communications equipment. The user processors act as originators and destinations of data communications packets. Packet data connections are through node controllers, which communicate with gateways, which are connected to a switching network via packet links. Control messages are communicated between node controllers, gateways, and an interchange control subsystem via various control message links. All control message processing and packet data transmissions are synchronized with a packet frame synchronization signal, and processing tasks performed by each of the network subsystems are pipelined so that they occur simultaneously. Service requests are queued in a central queue in the interchange control system. The synchronization and queueing simplify the control messages that are required to set up and release the connections.

Abstract: 1 Introduction 2 System Overview 3 Behavioral Transformations 4 Sequencing Graph and Resource Model 5 Design Space Exploration 6 Relative Scheduling 7 Resource Conflict Resolution 8 Relative Control Generation 9 Relative Control Optimization 10 System Implementation 11 Experimental Results 12 Conclusions and Future Work References Index

Abstract: High-speed networks still facilitate the advent of multimedia and distributed applications. An adaptive flow synchronization protocol that permits synchronized delivery of data to and from geographically distributed sites is presented. Applications include inter-stream synchronization, synchronized delivery of information in a multisite conference, and synchronization for concurrency control in distributed computations. The contributions of this protocol in the area of flow synchronization are the introduction of an adaptive synchronization delay, the flexibility to maintain multiple synchronization groups, and the use of a modular architecture that permits the client application to tailor synchronization calculations to its service requirements. Network protocols capable of maintaining network clock synchronization in the millisecond range are used. >

Abstract: Synchronous Parallel Environment for Emulation and Discrete-Event Simulation (SPEEDES) is a unified parallel simulation environment. It supports multiple-synchronization protocols without requiring users to recompile their code. When a SPEEDES simulation runs on one node, all the extra parallel overhead is removed automatically at run time. When the same executable runs in parallel, the user preselects the synchronization algorithm from a list of options. SPEEDES currently runs on UNIX networks and on the California Institute of Technology/Jet Propulsion Laboratory Mark III Hypercube. SPEEDES also supports interactive simulations. Featured in the SPEEDES environment is a new parallel synchronization approach called Breathing Time Buckets. This algorithm uses some of the conservative techniques found in Time Bucket synchronization, along with the optimism that characterizes the Time Warp approach. A mathematical model derived from first principles predicts the performance of Breathing Time Buckets. Along with the Breathing Time Buckets algorithm, this paper discusses the rules for processing events in SPEEDES, describes the implementation of various other synchronization protocols supported by SPEEDES, describes some new ones for the future, discusses interactive simulations, and then gives some performance results.

Abstract: A personal computer based, multimedia, data processing system includes a software solution to the problem of synchronizing two or more data streams which output data to two or more multimedia output devices. One stream is a master and each other stream is a slave. The master stream generates sync pulses that can be handled in two different synchronization methods, master-slave independent synchronization or master-driven slave synchronization. Sync pulses are generated with a predetermined granularity, and synchronization is achieved when a slave stream is out of tolerance. Adaptive resynchronization may be used to speed up or slow down a slave stream.

Abstract: Concurrent programming is a useful technique for structuring many important classes of applications such as interactive systems. This dissertation presents an approach to concurrent language design that provides a new form of linguistic support for constructing concurrent applications. This new approach treats synchronous operations as first-class values in a way that is analogous to the treatment of functions as first-class values in languages such as ML. The mechanism is set in the framework of the language Concurrent ML (CML), which is a concurrent extension of Standard ML. CML has a domain of first-class values, called events, that represent synchronous operations. Synchronous message passing operations are provided as the base-event values, and combinators are provided for constructing more complex events from other event values. This mechanism allows programmers to define new synchronization and communication abstractions that are first-class citizens, which gives programmers the flexibility to tailor their concurrency abstractions to their applications. The dissertation is organized into three technical parts. The first part describes the design and rationale of CML and shows how first-class synchronous operations can be used to implement many of the communication mechanisms found in other concurrent languages. The second part presents the formal operational semantics of first-class synchronous operations and proves that the polymorphic type system used by CML is sound. The third part addresses practical issues. It describes the use of CML in non-trivial applications, describes the implementation and performance of CML on a single-processor computer, and discusses issues related to the use and implementation of CML on a shared-memory multiprocessor.

Abstract: A quadrature amplitude modulation (QAM) communication system is provided in which data can be communicated in any one of a plurality of QAM modes, such as 16-QAM, 32-QAM, and 64-QAM. A receiver detects the particular QAM mode transmitted on a trial and error basis, by attempting to decode the received data using different QAM modes until a synchronization condition is detected. The synchronization condition can require that a plurality of different synchronization tests be met. In a specific embodiment, a first synchronization test is met when a renormalization rate of a trellis decoder is below a threshold value. A second synchronization test is met when a first synchronization word is detected in the received data. A third and final synchronization test is met when a second synchronization word is detected in the received data. In order to reduce the cost of the receiver, most of the QAM mode dependent components are implemented using look-up tables stored in PROMs.

Abstract: We analyse how inheritance of synchronization constraints should be supported. The conclusion of our analysis is that inheritance of synchronization constraints should take the form of incrementally more restrictive constraints for derived subclasses. Our conclusion is based on the view that combinations of behavior in object-oriented languages yield subclasses that extend superclass behavior. We give a notation for describing synchronization constraints. In our notation, synchronization constraints can be inherited and aggregated. We present a number of examples that illustrate the fundamental concepts captured by our notation. Synchronization constraints are described as restrictions that apply to invocation of methods. Application of restrictions is pattern-based, which allows the same restriction to apply to multiple methods and multiple restrictions to apply to the same method.

Abstract: In a hybrid drive for a motor vehicle, a three-phase machine fed by a three-phase converter is coupled via the layshaft of the gearbox to a conventional internal-combustion engine drive train. Both the internal combustion engine and the three-phase machine can be of conventional design. In addition to the known operating modes of a hybrid drive, the three-phase machine serves as a synchronization aid for the gear change in that the layshaft is accelerated in a suitable manner during the shifting operation. As a result, the mechanical synchronization devices in the gearbox have virtually no friction work to perform and can be of correspondingly smaller dimensions.

Abstract: A central-site (100) has located within it a synchronization system for purposes of backing-up a GPS external synchronization system. The central-site (100) is coupled to a plurality of base-sites (102, 103) which are required to be synchronized to one another. When the GPS signal is lost, the synchronization system within the central-site (100) allows the plurality of base-sites (102, 103) to maintain synchronization to one another. In this manner, the necessity for a synchronization system within each of the plurality of base-sites (102,103) is eliminated.

Abstract: Membership information is used to provide a consistent, system-wide view of which processes are currently functioning or failed in a distributed computation. This paper describes a membership protocol that is used to maintain this information. Our protocol is novel because it is based on a multicast facility that preserves only the partial order of messages exchanged among the communicating processes. Because it depends only on a partial ordering of messages rather than a total ordering, our protocol requires less synchronization overhead. The advantages of our approach are especially pronounced if multiple failures occur concurrently.

Abstract: Esterel is a synchronous concurrent programming language for reactive systems (controllers, protocols, man-machine interfaces, etc.). Esterel has an efficient software implementation based on a well-defined mathematical semantics. I present a new hardware implementation of the pure synchronization subset of the language. Each program generates a specific circuit that responds to any input in one clock cycle. The circuit is shown to be semantically equivalent to the source program. The hardware translation is effectively implemented and used on the programmable active memory Perle0 developed by J. Vuillemin and his group at Digital Equipment.

Abstract: In a QAM communication system, a novel synchronizing sequence of symbols added to the information channel simplifies acquisition of timing and synchronization by a receiver. Such synchronization vector provide signals for improved AFC control control signal generation.

Abstract: This paper deals with problems in schedule synchronization for public transit networks. First we reformulate the problem of minimizing waiting times of passengers changing communication routes at certain transfer stations in a network. In this problem all transit lines only meet at certain points or transfer stations. A second problem, in addition, considers the case where different lines partly use the same tracks implicating that security distances have to be observed.

Abstract: A data reading and image processing system for a video entertainment system with a CD-ROM capability is disclosed with a pair of separate computer systems that are controlled through a controller for accessing data from a memory unit. A first computer system can control the reading of data and the storing of the data in the memory unit in coordination with a first synchronization time period while the second computer system can control the processing of video data signals in an image processing circuit during a second synchronization time period. The data can be appropriately enabled to a position within the memory unit to assist in parallel processing by both computer systems.

Abstract: A method for graphically representing binary data in a condensed, machine-readable form, includes forming a pattern of information-carrying frame and synchronization lines defining a geometric reference system which forms boundaries of one or more data fields. The reference system carries machine-readable marks such as a bar code identifying the pattern as a data-field reference system and providing orientation and other information. The reference system also includes synchronization lines forming boundaries of each data field and providing a location reference. Within the reference system the data field has dot locations functioning as data-transmission elements. Each location has or lacks a mark, representing a "1" or "0" binary bit. Each data element location has a known geometric relationship to the synchronization lines of the reference system so that coordinates of each individual mark can be determined precisely.

Abstract: — Shared-memory parallel programs are often designed to be deterministic, both in their final results and intermediate states. However, debugging such programs requires a mechanism for locating race conditions or violations of the intended determinacy when they occur. This paper answers a previously open question by presenting the first precise, efficient algorithm for dynamically detecting race conditions in programs that use non-trivial synchronization. We address Post/Wait synchronization, the most powerful type of synchronization for which efficient race detection is possible. Our algorithm computes the order in which synchronization operations in the execution are guaranteed to have occurred. Using this information race conditions can be detected either post-mortem or on-the-fly. Previous work has addressed either simpler types of synchronization, approximations to race detection, or a different (and easier to detect) type of race.

Abstract: A method and system for synchronizing the presentation of data from different, but related, sources in different windows of a computer display. Data is positioned using duplicate sectional names that are in each of the data sources that are being synchronized. Even though the sectional names in each data source are the same, the contents of the sections can be different, independent, and unrelated. Multiple views of a single data source in different windows can be synchronized, showing data from many different locations within each data source. This allows authors and content experts to simultaneously show data from dissimilar data sources that have a logical connection, such as footnotes or commentary to a text, translations of a text, or updates to a read-only file.

Abstract: Optimistically synchronized parallel discrete-event simulation is based on the use of communicating sequential processes. Optimistic synchronization means that the processes execute under the assumption that synchronization is fortuitous. Periodic checkpointing of the state of a process allows the process to roll back to an earlier state when synchronization errors occur. This paper examines the effects of varying the frequency of checkpointing on the time and space needed to execute a simulation. The results presented in this paper were obtained from the simulation of closed stochastic queueing networks with several different topologies. Various process scheduling algorithms and message cancellation strategies are considered. The empirical results are compared with analytical formulae predicting time-optimal checkpoint intervals. It is shown that the time-optimal and space-optimal checkpoint intervals are not the same. Furthermore, a checkpoint interval that is too small adversely affects space more than time; whereas, a checkpoint interval that is too large adversely affects time more than space.

Abstract: The authors consider a new dimension to the problem of loop scheduling on shared-memory multiprocessors: communication overhead caused by accesses to nonlocal data. It is shown that traditional algorithms for loop scheduling, which ignore the location of data when assigning iterations to processors, incur a significant performance penalty on modern shared-memory multiprocessors. The authors propose a loop scheduling algorithm that attempts to simultaneously balance the workload, minimize synchronization, and colocate loop iterations with the necessary data. They compare the performance of this algorithm to that of other known algorithm using four representative applications on a Silicon Graphics multiprocessor workstation, a BBN Butterfly, and a Sequent Symmetry, and they show that the algorithm offers substantial performance improvements, up to a factor of 3 in some cases. They conclude that loop scheduling algorithms for shared-memory multiprocessors cannot afford to ignore the location of data, particularly in light of the increasing disparity between processor and memory speeds.

Abstract: A computer-based method and program for improving a design of a circuit through analysis of a computer stored model of the circuit. Individual synchronization points are identified in the circuit at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at the synchronization point. The timing of the circuit is verified based on the individual synchronization points.

Abstract: This thesis addresses theoretical and practical aspects of the dynamic detecting and debugging of race conditions in shared-memory parallel programs. To reason about race conditions, we present a formal model that characterizes actual, observed, and potential behaviors of the program. The actual behavior precisely represents the program execution, the observed behavior represents partial information that can be reasonably recorded, and the potential behavior represents alternate executions possibly allowed by nondeterministic timing variations. These behaviors are used to characterize different types of race conditions, general races and data races, which pertain to different classes of parallel programs and require different detection techniques. General races apply to programs intended to be deterministic; data races apply to nondeterministic programs containing critical sections. We prove that, for executions using synchronization powerful enough to implement two-process mutual exclusion, locating every general race or data race is an NP-hard problem. However, for data races, we show that detecting only a subset of all races is sufficient for debugging. We also prove that, for weaker types of synchronization, races can be efficiently located. We present post-mortem algorithms for detecting race conditions as accurately as possible, given the constraint of limited run-time information. We characterize those races that are direct manifestations of bugs and not artifacts caused by other races, imprecise run-time traces (causing false races to appear real), or unintentional synchronization (caused by shared-memory references). Our techniques analyze the observed behavior to conservatively locate races that either did occur or had the potential of occurring, and that were unaffected by any other race in the execution. Finally, we describe a prototype data race detector that we used to analyze a sample collection of parallel programs. Experiments indicate that our techniques effectively pinpoint non-artifact races, directing the programmer to parts of the execution containing direct manifestations of bugs. In all programs analyzed, our techniques reduced hundreds to thousands of races down to four or fewer that required investigation.

Abstract: Synchronization of an architectural model of a computer architecture and a behavioral model of an implementation of the architecture for functional verification of the implementation. A communication channel is established between the two models through which simulation control and state information can be communicated and both models are available for simulating. Synchronization points in the models' executions are identified, and a synchronizer is implemented which instructs each model to simulate to a synchronization point and report relevant state information. The synchronizer can also verify state information from the two models in real time, flag errors, or instruct the architectural model to modify its state either to match known errors in the behavioral model or to match correct behavior to an asynchronous event.