Abstract: Constructing reliable programs for distributed processing systems is a very difficult task. Actions (transactions), indivisible units of work, can simplify this process by providing uniform treatment of failures and preventing interference. These units of work can also be nested, further controlling the scope of concurrency and failures. The atomicity provided by actions is an important tool for building reliable decentralized systems. Actions manipulate pieces of data called objects. Objects are usually treated as uninterpreted (bit strings). However, treating all objects in this fashion can result in unacceptable concurrency or high recovery overhead. In order to take advantage of actions in the widest possible context, it is necessary to consider operations on generalized objects (instances of abstract data types). This report presents a general architectural model for reliable decentralized systems constructed using actions and objects. We include one prototype design created from the model. We also include practical algorithms necessary to implement this design. We present a nested action management algorithm that, to our knowledge, is the first such algorithm to separate remote call semantics from action units. It also guarantees that orphans, computational parts of actions that will be eventually aborted, view consistent system states. We describe a design for synchronization and recovery that is oriented toward a programming-based view of objects (as well as simple data). We demonstrate the usefulness of our results through typical reliable programming problems. Availability is another important dimension of distributed systems. We describe a novel collection of simple, yet very robust, replication algorithms which can increase data availability. Algorithms from this suite can be customized to balance particular tradeoffs required in different application systems. The efficiency of the algorithms depends on the acceptability of weak consistency conditions in the applications. One member of this suite is formally modelled and proven correct. The others follow in a straightforward manner.

Abstract: In this report we give a detailed presentation of how monitors can be implemented on the HEP using a simple macro processor. We then develop the thesis that a small body of general-purpose monitors can be defined to handle most standard synchronization patterns. We include the macro packages required to implement some of the more common synchronization patterns, including the fairly complex logic discussed in a previous paper. Code produced using these macro packages is portable from one multiprocessing environment to another. Indeed, by recoding the set of basic macros (about 100 lines of code for the Denelcor HEP), most programs that we are new writing could be moved to any similar multiprocessing system.

Abstract: Three notations for concurrent programming are compared, namely CSP, Ada, and monitors. CSP is an experimental language for exploring structuring concepts in concurrent programming. Ada is a general-purpose language with concurrent programming facilities. Monitors are a construct for managing access by concurrent processes to shared resources. We start by comparing "lower-level" communication, synchronization, and nondeterminism in CSP and Ada and then examine "higher-level" module interface properties of Ada tasks and monitors.

Abstract: Independent asynchronous bus master devices share a common bus with control lines serially connecting each bus master in a daisy-chain contiguration A Bus Acknowledge signal is received by a local bus master which is thereby enabled to seize control of the bus without an input synchronization delay by first inhibiting synchronization means to prevent the passage of the Bus Acknowledge signal to a downstream device for a period of time sufficient to stabilize an output signal indicating such passage In that manner, the output signal may be used to control the immediate enabling of local bus seizure thereby avoiding local synchronization delay

Abstract: A time-division switching unit for connecting a desired channel of a desired one of a plurality of input highways to a desired channel of a desired one of a plurality of output highways is disclosed. A frame synchronization circuit of the time-division switching unit variably delays signals of the input highways within one channel period, writes the signals to a speech memory for each channel, modifies write addresses to the speech memory to attain frame synchronization, extracts frame synchronization signals of the respective highways from the input and output of the speech memory, and controls the amount of delay within one channel period and the amount of address modification by the extracted synchronization signals.

Abstract: Virtually all the algorithms now being used for network simulation, tracking and optimization are synchronous. They cannot be broken into parallel processes for concurrent execution without inserting a number of synchronization points. The first process to reach a synchronization point must wait for the others to catch up. The resulting delays and communication overheads often grow rapidly with the number of processors. When this happens, large numbers of processors can be used with advantage only if the synchronous algorithm is replaced with an asynchronous procedure. This is not always easy. Asynchronous procedures tend to be counter intuitive, difficult to construct and difficult to analyze. To reduce these disadvantages we will develop concepts useful in thinking about asynchronous procedures, discuss a model after which they may be patterned, introduce some new convergence results and presents some illustrations of how to construct asynchronous procedures. Finally, we will discuss an important application area-contingency constrained optimum flows.

Abstract: The computer hardware executive is a special purpose associative processorhich interfaces to the memory bus of a digital computer to provide high-speed execution of executive functions. These functions include task registration, task synchronization, normal, time-dependent and time-critical event registration and triggering, hierarchical event-to-semaphore translation, and buffer allocation. The programmer invokes an executive function by accessing the address in the hose computer address space dedicated to that function. The data written to or read from that address is the function operated or result, respectively. The hardware executive maintains task and event tables internally within its associative memory. The memory is organized such that the same field bit position of all table entries is accessed in parallel within a microinstruction cycle. Searches are performed by sequencing through the bit positions of interest. The computer hardware executive also contains an internal clock for comparison against time-dependent and time-critical event registrations. The executive function algorithms are executed by an internal microprogram.

Abstract: A speech recognizer is disclosed which includes a number of processors (110,130, 140,150,160) each having a shared memory (406) associated therewith. Each processor performs local processing tasks on data stored in the associated shared memory. The data stored is distributed by direct memory access during and without interfering with local processing of the remaining data stored in the shared memories. A plurality of circuits are connected to a shared data bus (412) for effecting the data transfer across the shared data bus. A remote controller (447) controls transfer of data across a remote bus (450). A shared controller (440) includes synchronization circuitry (1100) for synchronizing shared data bus requests with the timing of the local processor, and priority circuitry (1000) to insure that the local processor always has access to the shared memory (406) through the shared data bus (412) without waiting. When used in continuous speech recognition, a front end processor (110) is employed for converting digital spectral speech data to frames of parametric data more suitable for further speech processing; at last two template processors (130, 140, 150) are employed to store the recognizable vocabulary as templates and for comparing the frames of parametric data individually with the stored templates; and a master processor (160) is employed to transfer new frames of parametric data to the template processors and to redistribute templates among the template processors for more efficient processing in response to analysis of the results of template comparisons.

Abstract: The demand for large-scale multiprocessor systems has been substantial for many years. The technology for fabrication of such systems is available, but attempts to extend traditional architectures to this context have met with only mild success. The authors hold that fundamental aspects of the Von Neumann architecture prohibit its extension to multiprocessor systems; they pose dataflow architectures as an alternative. These two approaches are contrasted on issues of synchronization, memory latency, and the ability to share data without constraining parallelism. 12 references.

Abstract: Suckling post-partum cows treated for oestrous synchronization exhibited oestrus and became pregnant earlier in the mating period than untreated cows. Combined treatment with a progesterone-releasing device and prostaglandin F 2α synchronized oestrus in a greater proportion of the cows than treatment with prostaglandin F α alone ( P

Abstract: Disclosed is a method for synchronizing multiple data processing systems that control the process BEITEN identical programs bear in stand-by mode. Here are to be executed only fers triggered interrupts data Trans, when all data processing systems have achieved the same status in the program processing. This state is by counting of instructions and comparing the counter values ​​in such determ with that the further processing of instructions is prevented by the occurrence of an interrupt for the data processing system with the highest counter reading, and the other data processing systems continue processing until they have the same have reached count. Only after the synchronous data transfer will be redeemed. An apparatus for performing the method is provided in which the necessary components are combined in a monitoring unit.

Abstract: A circuit for detecting a proper locked state between the output of a phase-locked loop clock generating circuit and a timing component of a received composite signal containing both digital information and the timing component. An internal synchronization pulse signal is produced directly in response to the output of the phase-locked loop, and a frame synchronization sequence detection pulse signal is produced by detecting the occurrence of frame synchronization sequences in the composite signal. The internal synchronization pulse signal and the frame synchronization sequence detection pulse signal are compared to determine whether or not they are in time coincidence. If they are not, corresponding to an improperly locked state, a synchronization hunting controller controls the internal synchronization pulse generator to shift the phase of the internal synchronization pulse signal until time coincidence occurs. The output of the synchronization hunting controller is also used a lock detection signal. A frame synchronization signal is produced by delaying the output of the internal synchronization pulse generator.

Abstract: Many people are trying to be smarter every day. How's about you? There are many ways to evoke this case you can find knowledge and lesson everywhere you want. However, it will involve you to get what call as the preferred thing. When you need this kind of sources, the following book can be a great choice. distributed computer systems synchronization control and communication is the PDF of the book.

Abstract: In the process of learning how to write code for the Denelcor HEP, we have developed an approach that others may well find useful. We believe that the basic synchronization primitives of the HEP (i.e., asynchronous variables), along with the prototypical patterns for their use given in the HEP FORTRAN 77 User's Guide, form too low-level a conceptual basis for the formulation of multiprocessing algorithms. We advocate the use of monitors, which can be easily implemented using the HEP primitives. Attempts to solve substantial problems without introducing higher-level constructs such as monitors can produce code that is unreliable, unintelligible, and restricted to the specific dialect of FORTRAN currently supported on the HEP. Our experience leads us to believe that solutions which are both clear and efficient can be formulated using monitors.

Abstract: Publisher Summary This chapter describes the specification and implementation of abstract data types (ADT). A data structure is to be identified with the operations that are applicable to it, and the only way to generate an instance of the data structure is by means of a sequence of applications of the operations. This is called data abstraction. The chapter deals with the problems associated with data abstraction, including the traversible stack syndrome, functional and procedural programming, and synchronization problems. The chapter distinguishes between the operational approach and the algebraic approach of specifications. Algebraic specifications provide clear descriptions of the computational objects in a self-contained way. An operational specification depends on a representation domain. The chapter discusses modularization, that is, the decomposition of a program into a set of functionally distinct units, and the importance of data types with respect to program correctness, and why data types should be defined in terms of operations.

Abstract: As part of our research in the Archons [Jensen 82] project on decentralized computers, we have developed a relational model of data consistency to replace the conventional serialization model for reasoning about the relationships among distributed system data objects in general and state variables in particular. We not only permit but encourage such relationships to be probabilistic, in the interest of efficiency. This model leads to a new formulation of co-operating processes, and thence to the notion of co-operating transactions: co-operating processes whose actions are made atomic for the sake of reliability. We believe that co-operating processes are valuable in a computer network, but essential in a decentralized computer [Jensen 82] where the conceptually singular but physically dispersed global operating system requires a transaction facility in the kernel [Jensen 80]. These ideas are illustrated by examples from our initial experience in applying the model to the Accent network operating system and other system software of the Spice personal computing network. This document is intended to be an overview of the synchronization effort in the Archons project, and future publications will elaborate on many of the individual points touched on here.

Abstract: The GEM model of concurrent computation is presented. Each GEM computation consists of a set of partially ordered events, and represents a particular concurrent execution. Language primitives for concurrency, code segments, as well as concurrency problems may be described as logic formulae (restrictions) on the domain of possible GEM computations. An event-oriented method of program verification is also presented. GEM is unique in its ability to easily describe and reason about synchronization properties.

Abstract: In this paper we consider variations on the binary search algorithm when placed in the context of a multiprocessing environment. Several organizations are investigated covering the spectrum from total independence (or free competition for access to common resources) to cooperation as in SIMD architectures. It is assumed that the two main sources of overhead are memory interference and interprocessor synchronization. An organization combining interference-free access to memory by implicit synchronization and a small degree of cooperation yields the best results.

Abstract: Structure for reproducing a copy from an original by driving an original past a light source and light sensors to develop signals in the sensors representative of intelligence on the original which it is desired to copy, driving a copy member past printers in synchronization with the driving of the original and actuating the printers in accordance with the signals sensed by the sensors. The sensors and printers are modular. Amplifiers may be provided between the sensors and the printers, and signals from the sensors may be stored prior to printing in response thereto. The reproduction may be different in size than the original and/or in color.

Abstract: A parallel MIMD type processor for use in image processing applications on board satellites is described. Emphasis is given to the application requirements in terms of processing power, type of parallelism, communication need and to the impact of these requirements on the architecture design. The choice of a MIMD processor with a ring bus, the convenience of a multiple bus structure, the definition of the bus protocole, the synchronization mechanism and the typical performances are presented as successive choices and discussed in regard of the requirements. Possibilities and limits of the architecture are carefully analyzed: Typical examples of efficiently implementable applications in other fields of image processing are given. But limits of the structure are pointed out for other types of parallel processing.

Abstract: In his paper "Communicating Sequential Processes," Hoare suggested the use of the input/output construct and Dijkstra's guarded commands for handling the task of communication and synchronization in distributed systems. Hoare's proposal was intended for programming general parallel systems; as a result, little consideration was given by Hoare to the question of how his mechanisms could be utilized in the construction of reliable dynamic resource management schemes. In this paper, we examine this problem and propose several simple extensions to Hoare's constructs that will make the extended Communicating Sequential Processes concept more suitable for the handling of such management schemes.

Abstract: This paper presents an improved approach to the design of software for hard-real-time systems. The software for such systems is usually difficult to change because of constraints imposed by the need to meet absolute deadlines on processors with limited memory capacity. Dijkstra and others have shown that the concept of cooperating sequential processes can be used to improve the structure of software when concurrency is present. However, their techniques do not (1) deal with real-time deadlines, (2) are not efficient in their use of processor time and memory, and (3) do not allow simple efficient synchronization in the complex situations that arise in typical embedded systems. This paper presents a number of refinements to the basic concept that allow its use in hard-real-time embedded software. The three key ideas are, (1) a multi-level approach that allows convenient synchronization without a penalty in real-time response, (2) the use of a pre-run-time scheduler to allow more efficient use of resources, and (3) a new synchronization scheme that is both simple and general.

Abstract: A standard for BASIC is nearing completion. An integral part of that standard is a module of the language addressing the needs of real-time applications. This paper describes the features of real-time BASIC, highlighting the concurrency aspects, the mechanisms provided for inter-process communication and synchronization, and for communication with the hardware system. An example showing how the language may be used to control the environment and pump water from a mine shaft is included. The use of the language with a distributed control system is also discussed.

Abstract: T HE GENERAL procedures adopted in the design of the Integrated Service Digital Terminal (ISDT) are described. The ISDT accommodates multiple-bit-rate signals from various sources, as a step towards realizing the ISDN. First, the fundamental ISDT concept is introduced, and the signal source bit-rate series and cross-connect unit are discussed as network parameters. Secondly, a systematic proposal is made which takes into consideration multiplexer module classification and the multiplexing algorithm. Thirdly, a multiplexer realization procedure and its cost effectiveness are described. Finally, the total ISDT operation system concept is introduced. The construction of an integrated digital network began in 1977 with the introduction of a digital data network which carried data in the form of a digital signal over one digital transmission link [I]. Subsequently, telephone network digitalization was initiated in the expectation that common usage of telecommunications facilities could be realized for various kinds of services in the future. In this process, the network synchronization technique was established up to the secondary digital stage (DS-2,6.312 Mb/s). In addition, the intra-office 8-kHz phase alignment method was developed. By synchronizing a digital network, it is possible to introduce a direct time-slot interchange between different data

Abstract: Presante the invention relates to the synchronization signal regeneration (Hs) for writing and / or reading the recorded digital data or recording on an optical information carrier. According to the invention, the synchronization signals (H In a preferred embodiment, specific data and useful information data is encoded according to the NRZ code, the specific data being associated with non-used pulse durations in the NRZ code for the registration of information data. Specific data can be recorded with time multiplexing of digital information data, or in a preferred variant, as flags in sites regularly spaced tracks definissante therebetween areas for recording blocks data. The registration of these flags can be done prior to any registration of digital information data in the form of pre-etching. The synchronization signals (H Application especially in computers, optical memory systems random access.

Abstract: Data abstraction and inheritance, some of the most important features in constructing a large, clean software system, in a logic programming language Prolog/KR, an expansion of Prolog, are described. First two kinds of processes are added; one is called NPO, which is mainly used to implement a generator, the other is called CPO, which is mainly used to implement an abstract data object. Then synchronization features are added to implement abstract data types that can be used concurrently. Using this feature it is possible to employ pipes for communications among processes. Finally, inheritance mechanism is added to define hierarchies among objects.