Abstract: 1. Motivations, objectives and characterization of distributed systems.- 2. Distributed system architecture model.- 3. Interprocess communication layer: Introduction.- 4. Hardware interconnection technology.- 5. Link level.- 6. Hierarchy.- 7. IPC interface and end-to-end (transport) protocol design issues.- 8. Distributed control.- 9. Identifiers (naming) in distributed systems.- 10. Protection.- 11. Atomic transactions.- 12. Synchronization.- 13. Multiple copy update.- 14. Applications and protocols.- 15. Error recovery.- 16. Hardware issues.- 17: Hardware/software relationships in distributed computer systems.- 18. The national software works (NSW).- 19: Ethernet, pup and violet.- 20. Conclusion.- References.

Abstract: A new proposal for synchronization and communication in parallel programs is presented. The proposal, called synchronization resources, combines and extends aspects of procedures, coroutines, monitors, communicating sequential processes, and distributed processes. It provides a single notation for parallel programming with or without shared variables and is suited for either shared or distributed memory architectures. The essential new concepts are operations, input statements, multiple processes and resources. The proposal is illustrated by solving a variety of parallel programming problems. Key Words and Phrases: parallel programming, processes, synchronization, process communication, monitors, distributed processing, programming languages, operating systems, data bases. CR Categories: 4.20, 4.22, 4.32, 4.35

Abstract: An information structure called a semaphore serves as a signalling mechanism in process synchronization. The semaphore is used to relate a process and an event which do not appear simultaneously. In accomplishing this, the semaphore is capable of storing the presence of events or resources waiting for processes or, alternatively, the presence of processes waiting for events or resources via a queue.

Abstract: Studies were conducted in Georgia, Illinois and Maryland, representing three geographical regions of the United States, to determine the dose range of the orally active progestin, allyl trenbolone (RU-2267), for effective synchronization of estrus in swine. Animals that had displayed estrus at least once were group-fed for 18 days 5, 10, 20 or 40 mg of RU-2267 incorporated into a daily diet of 1.8 or 2.3 kg of feed. The numbers of gilts given each respective dose were eight, eight, eight and seven in Georgia, and six, five, six and six in Illinois. Five pigs received each dose in Maryland. Five primiparous sows were also treated with each dose in Maryland. Estrus was checked daily with a boar, and ovaries were examined by laparotomy 4 to 10 days after the estrous period following treatment or 15 to 24 days after the end of treatment in those animals that failed to display estrus. In Maryland, the interval from end of treatment to estrus (interval to estrus) differed (P<.05) between gilts (5.4 -+ .3) and sows (6.0 -+ .2) fed the 20-mg dose; but no other age differences were detected, and, as a result, data for gilts and sows were combined. The percentage of animals displaying a post-treatment estrus (estrous response) and the average number of corpora

Abstract: A previous paper compared the mechanisms for process communication in Hoare's communicating sequential processes and in Brinch Hansen's distributed processes, by both qualitative and quantitative analyses This paper extends these analyses to the corresponding features for communication between tasks in Ada The similarity between Ada's features and Hoare's proposals is confirmed, but some limitations on non‐determinism in Ada are noted

Abstract: The traditional mechanism for maintaining a list of pending events in a discrete event simulation is the simple linked list. However, in large scale simulations this list often becomes cumbersome to maintain since the number of pending events may become quite large. As a result, the execution time required by the simple linked list is often a significant portion of total simulation time. Several papers have been published suggesting improved synchronization procedures. The most efficient procedures reported are the time-indexed procedure and the two-level procedure. Both methodologies are much more efficient than simple linked lists; however, neither has been adopted by a general purpose simulation language. Further, both procedures require external parameter definition, which is a major handicap to their adoption by a general purpose language. This paper introduces a new sychronization procedure, the two-list procedure, which is much faster than simple linked lists for large pending event files. This procedure was designed for implementation in Fortran, and properly implemented it is transparent to the user. Thus it is ideal for adoption by general purpose simulation languages.

Abstract: A data stream is received from a medium. This stream consists of synchronization words and data words. The synchronization words are either identical or one the inverse of the other when they are correctly received. Between two synchronization words a fixed number of n data words is present. The information received is always consecutively stored in a buffer memory. The buffer memory has connected to it a detection device for generating an instantaneous synchronization signal by way of a majority decision on at least three correctly received synchronization words. Preferably, the buffer memory is a shift register comprising a data output which is situated approximately 1/2n data words +1/2 synchronization word beyond the center of the shift register when n has an even value.

Abstract: An information reporting system is disclosed wherein a plurality of remote stations each receive synchronization signals from a master station, the synchronization signals initiating a timing mechanism in each remote station for dictating the time slot in which each remote station can transmit its information, each time slot occurring at a substantially different point in time, a master station having a synchronization generator for generating the synchronization signals and an indicator for indicating the information received from the remote stations, and a communication channel for interconnecting the remote stations and the master station.

Abstract: This is an elaboration of the paper `Synchronization and matching in redundant systems' by Davies and Wakerly (ibid., vol.27, p.531-9, 1978). The design of voters for synchronization is strongly dependent on the signaling convention used. This correspondence presents voter designs for three different signaling conventions (transition, level, and pulse). The issue of improved voter performance is also addressed.

Abstract: A plurality of thermal head assemblies can be arranged around a single backing roller to minimize the distance between recording stations. Synchronization marks recorded on the paper at a first station can be detected between recording stations to control the timing of image recording at the later stations.

Abstract: The semantics of a pair of synchronization primitives is characterized by three fundamental axioms: boundedness, progress, and fairness. The class of primitives fulfilling the three axioms is semantically defined. Unbuffered communication primitives, the symmetrical P and V operations, and the usual P and V operations are proved to be the three instances of this class. The definitions obtained are used to prove a series of basic theorems on mutual exclusion, producer-consumer coupling, deadlock, and linear and circular arrangements of communicating buffer-processes. An implementation of P and V operations fulfilling the axioms is proposed.

Abstract: This paper considers a fixed (possibly infinite) set π of distributed asynchronous processes which at various times are willing to communicate with each other. We describe probabilistic algorithms for synchronizing this communication with boolean “flag” variables, each of which can be written by only one process and read by at most one other process. With very few assumptions (the speeds of processes may vary in time within fixed arbitrary bounds, and the processes may be willing to communicate with a time varying set of processes (but bounded in number), and no probability assumptions about system behavior) we show our synchronization algorithms have real time response: If a pair of processes are mutually willing to communicate within a constant time interval, they establish communication in that interval, with high likelihood (for the worst case behavior of the system). Our communication model and synchronization algorithms are quite robust. They are applied to solve a large class of real time resource synchronization problems, as well as real time implementation of the synchronization primitives of Hoare's multiprocessing language CSP.

Abstract: This paper describes a proposal for a modification to the language Modula. The modification was motivated by a desire to bring to the language the ability to build hierarchical systems and to support program verification efforts. In the modified language, called SB-Mod, modules are grouped into levels and calls are permitted from the modules of one level to those of a higher level. Verification is supported through a set of clearly described synchronization constructs and by restricting the flow of information between levels. A result of this is that levels do not interfere with each other and can be treated separately for purposes of verification. In considering modifications, an attempt was made to provide the user with a variety of control mechanisms, while at the same time avoiding situations in which excessive run-time overhead would be incurred.

Abstract: Data-flow models are well-known as representations for achieving asynchronous and concurrent execution of applicative programs. Heretofore, the main focus of interest in data-flow models has been on determinate and value-oriented computations; efforts at handling indeterminate computations, especially the problems of resource control, have been few. This dissertation examines some practical and theoretical aspects of resource control in one particular class of data-flow models. The execution model here is based on a demand-driven principle, and the high-level programming language is based on the concept of 'function graphs', and is thus called Function Graph Language (FGL). The main emphasis of this work is on a reliable, efficient, and flexible approach to defining shared data objects and synchronization of the processes that use them. It is shown that a demand-driven model of execution provides many computational advantages for designing primatives for synchronization. In keeping with the applicative style, an expression-based language, called Resource Expressions, is introduced, so that properties of synchronization, such as mutual exclusion, priority, etc., may be specified in a high-level form. The formal semantics of this language are based on the concept of 'execution graphs'. The translation of Resource Expressions into the primitives for implementation and its correctness proof are presented. Using the specifications in this abstract implementation, an actual implementation in terms of the primitive operators is subsequently derived. This implementation takes advantage of the demand-driven model is representing potentially-infinite execution graphs, and also exploits concurrency in the arbitration and execution of operations.

Abstract: The Thue-Morse sequence (TMS), the "parity check" sequence formed on a normal binary counter, has been proposed as a vehicle for comma-free synchronizatin of binary counters. This note reports further work on the TMS as a vehicle for commafree synchronization of binary counters. Specifically, we present a new synchronization algorithm and a way to implement the algorithm via PSK encoding/DPSK decoding, and we examine and comment on the TMS/BPSK spectrum.

Abstract: Two concurrency control mechanisms, the SDD-1 system and Dynamic Timestamping Method, are evaluated in terms of protocol synchronization delays and average transaction response time by using simulation. Relationship among average protocol synchronization delay, average transaction response time, average 10 service delay, communication delay, and other system parameters is analyzed by using regression analysis. The statistical distribution functions of transaction response times and synchronization delays are then examined to see if they fit exponential, erlangian, or some other distribution functions.

Abstract: This dissertation addresses the extension of traditional dataflow modeling to include specifications to allow additional control over the execution environment. Three major studies are presented: (1) a comparative analysis of several proposed and existing dataflow models and architectures, (2) the specification of several extensions for generalizing traditional abstract dataflow models and providing the opportunity to express greater parallelism, and (3) the design and implementation of an evolutionary test bed for realizing the simulation of dataflow programs and systems. The extensions to the abstract dataflow model include: (1) a generalized firing rule to eliminate unnecessary synchronization introduced by requiring all inputs to be available before enabling nodal execution, (2) a mechanism for obtaining a higher degree of parallelism through replication of nodes, (3) a concept of generalized termination detection and signaling useful in supporting replication and streaming, and (4) the description of methods for supporting shared data objects and interprocess communications in a multiple process dataflow environment. The dataflow simulator, DFSS, was developed in support of this work and is a highly generalized facility for realizing the execution, debugging, and metering of dataflow programs.

Abstract: N integrated digital network which combines digital transmission and switches can provide efficient and economical paths to carry analog ~ and digital information. Digital networks have been developed for data or voice services, and it is believed that they may be extended in the future to apply to the integrated services digital network (ISDN). Network synchronization is an essential technique in constructing an integrated digital network. In several countries, the domestic network synchronization systems have either been developed or are under development, These systems employ either the master-slave or mutual synchronization scheme. For the future international digital network, plesiochronous operation is recommended by the CCITT.

Abstract: The transmission and reception pattern generators are synchronized for all data ports operating at the same data rate throughout an entire TDMA system. This eliminates the necessity for bit stuffing to accommodate non-integral multiple data rate data ports and yet allows data activity compression operations to be carried out.

Abstract: The synchronization mechanism of the Ada Language is intended to provide a facility for tasks to synchronize their actions. Accept and select statements are the two main features of the language that deal with the issue of synchronization This paper points out one major problem that arises in connection with these features and proposes a possible solution to it.

Abstract: 1. A transmission system for transmitting packets of digital data arranged into bytes on a continuous-flow channel, the data packets (Bi) being individually inserted into transmission blocks (Pi) the beginnings of which are periodically transmitted, the period of the transmission of the beginnings of transmission blocks (Pi) being at least equal to the maximum length of a transmission block, characterized in that the beginning of each transmission block (Pi) comprises a synchronization pattern (Ei) constituted by a "bit" synchronization byte and a "byte" synchronization byte.

Abstract: A circuit is provided for synchronizing a transmitting/receiving station to the data network of a digital communications system having a correlation receiver in the relevant receiving device which supplies a correlation signal serving for synchronization purposes. The function of the correlation receiver is to implement the bit synchronization and block synchronization for the most favorable radio range from an asynchronous state, in the synchronous state to supply the adjustment criteria for the current radio range and, in the event of rebooking, to supply those of all the other possible radio ranges (indirect access to the adjusting elements via a computer). For this purpose, in the receiving device, the incoming non-generated items of received data are fed, on the one hand, to the correlation receiver and, on the other hand, to a regenerating device which can be set up by the signals of the correlation receiver. The correlation receiver comprises a signal output for the received pulse train setting-up (bit synchronization) and a signal output for block synchronization. The two signal outputs are connected to a computer. In addition, the signal output for the bit synchronization is connected to the regenerating device via a computer-control switch and via a phase pulse train shift device, whereas the signal output for block synchronization is connected thereto via a switch which is also controlled by the computer.

Abstract: PURPOSE:To prevent increment of hardware and cause ID numbers to correspond to synchronization to establish synchronization so many folds, by establishing synchronization only between instructions which require to keep sequential relations. CONSTITUTION:A WAIT instruction is separated into a synchronization start instruction POST assigned by an ID number and a synchronization end instruction WAIT assigned by an ID number to instruct synchronization. Vector load VL (instruction A) and VL (instruction B) are executed prior to execution of a vector load store VST (instruction F), and a VST (instruction C) is executed prior to execution of a VL (instruction G). The POST1 assigned by ID number 1 is prepared after instructions A and B, and the POST2 assigned by ID number 2 is prepared after the instruction C. The WAIT1 assigned by ID number 1 is prepared before the instruction F, and the WAIT2 assigned by ID number 2 is prepared before the instruction G, thus preventing increment of hardware and causing ID numbers to correspond to synchronization to establish synchronization so many folds.