Abstract: Synchronization of concurrent processes requires controlling the relative ordering of events in the processes. A new synchronization mechanism is proposed, using abstract objects called eventcounts and sequencers, that allows processes to control the ordering of events directly, rather than using mutual exclusion to protect manipulations of shared variables that control ordering of events. Direct control of ordering seems to simplify correctness arguments and also simplifies implementation in distributed systems. The mechanism is defined formally, and then several examples of its use are given. The relationship of the mechanism to protection mechanisms in the system is explained; in particular, eventcounts are shown to be applicable to situations where confinement of information matters. An implementation of eventcounts and sequencers in a system with shared memory is described.

Abstract: Path expressions are a tool for synchronization of concurrent processes. They are an integral part of the data abstraction mechanism in a programming language, and specify synchronization entirely in terms of the allowable sequences of operations on an object of the abstract data type. This paper describes an attempt to push the path expression synchronization construct along three dimensions - specification, verification, and implementation - into a useful theoretical and practical tool. We define Predicate Path Expressions (PPEs), which allow for a more convenient specification of many synchronization problems. The predicate is a powerful extension to path expressions that increases their expressiveness. We formally define the semantics of PPEs by a transformation to a corresponding nondeterministic program, thus allowing the use of known verification techniques for nondeterministic programs to be used for proving properties of the PPE and the data abstraction of which it is a part. We also describe our existing implementation, in Algol 68, of a data abstraction mechanism that incorporates PPEs.

Abstract: In recent years, many high-level synchronization constructs have been proposed. Each claims to satisfy criteria such as expressive power, ease of use, and modifiability. Because these terms are so imprecise, we have no good methods for evaluating how well these mechanisms actually meet such requirements. This paper presents a methodology for performing such an evaluation. Synchronization problems are categorized according to some basic properties, and this categorization is used in formulating more precise definitions of the criteria mentioned, and in devising techniques for assessing how well those criteria are met.

Abstract: Recent advances in technology have made the construction of general-purpose systems out of many small independent microprocessors feasible. One of the issue's concerning distributed systems is the question of appropriate language constructs for the handling of communication and synchronization. In his paper, "Communicating sequential processes," Hoare has suggested the use of the input and output constructs and Dijkstra's guarded commands to handle these two issues. This paper examines Hoare's concepts in greater detail by concentrating on the following two issues: 1) allowing both input and output commands to appear in guards, 2) sinple abstract implementation of the input and output constructs.

Abstract: An asynchronous system for transmitting digital data from a data origination station to a data utilization station over a communications path such as an ordinary long-distance telephone network is disclosed. The system includes circuitry for synchronizing and maintaining synchronization between the receiving circuits and the transmitting circuits and for correcting errors introduced by the communications path. Each data word transmitted has associated therewith a synchronization code comprising a stop bit and a start bit. During normal operation, the system is synchronized by detecting the start bit which precedes the information portion of each data word. Synchronization is maintained for several data words even though the start bit is not detected due to interference, for example, by an auto-synchronization signal which includes a pulse positioned within the time period during which the start bit would normally be detected. Additionally, should a predetermined number of successive data words arrive at the receiver with errors, the auto-synchronization signal is disabled based on the assumption that the errors are due to a loss of synchronization. The transmitter circuits then transmits two synchronizing words, each containing the synchronization code with all other bits having a logic "zero" level. The synchronization code of the two synchronizing words resynchronizes the system thereby restoring normal operation. That is, the system maintains normal synchronization even though interference destroys the start and/or stop bits of a number of successive words. Should this interference continue such that the automatic synchronization circuits can no longer maintain synchronization, the auto synchronization circuit is disabled and normal synchronization is restored by transmitting two special synchronization words, all without any loss of data.

Abstract: The present invention relates to a jacking system for use in the construction of buildings or other structures in which accurate control and synchronization of lifting points is required. The system is mainly used in lift-slab and lift-plate construction with permanent or removable columns and features an arrangement of converging control wires which activate sensing apparatus. The sensing apparatus controls hydraulic pumps placed at each or plural lifting points.

Abstract: An improved bus allocation system to control a time division multiplexed digital data bus used by a plurality of signal sources such as a number of digital processing components in a decentralized system in which there is no single entity controlling the bus. The system includes a mechanism for maintaining allocation synchronization under realistic, non-ideal conditions in which noise or other error producing interferences may be present. Each signal source is provided with a bus interface unit having an address counter which operates in conjunction with an allocation vector. The counters operate through a repeating cycle of counts and one or more of the counts in each cycle based on its allocation vector. Each address counter is synchronized during or following the receipt of a message using a unique comparison sequence of comparisons. By means of this system the value of all counters within the range of synchronization are made identical in response to a bus allocation synchronization signal. If a given address counter is off too many counts to be synchronized, the transmitter of the associated device is disabled until it can be re-synchronized by a later synchronization signal. Thus any device having a counter that is out of synchronization for any reason cannot transmit until such synchronization is restored. This prevents interference occasioned by more than one device using the bus at a given time.

Abstract: One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary

Abstract: A process is disclosed for frame synchronization in a time division multiplex system which, while ensuring a high degree of synchronization reliability, requires only a small transmission capacity. In accordance with the invention, before a synchronous state is reached, a synchronization alarm (SA=1) is given and the recognition of two consecutive synchronizing words (100010) defines the beginning of a test period (P). If synchronizing words (100010) are constantly received during this test period (P), the synchronization alarm (SA=1) is disconnected. If only one single synchronizing word (100010) is not recognized during the test period (P), the synchronization alarm continues. Commencing from the synchronous state, the synchronization alarm is given if a plurality of synchronizing words are not recognized (FIGS. 3 to 6).

Abstract: In this paper, a new approach to coordinating accesses to shared data objects is described. We have observed that synchronization of accesses to shared data and recovering the state of such data in the case of failures are really two sides of the same problem—implementing atomic actions on multiple data items. We describe a mechanism that solves both problems simultaneously in a way that is compatible with requirements of decentralized systems. In particular, the correct construction of a new atomic action can be done without knowledge of all other atomic actions in the system that might execute concurrently. Further, the mechanisms degrade gracefully if parts of the system fail—only those atomic actions that require resources in failed parts of the system are prevented from executing.

Abstract: Fiber optic signals of the unipolar Manchester type undergo translation by a logic circuit system to a bipolar type. The system is capable of differentiating between the occurrence of a message gap and valid data or synchronization signals.

Abstract: An approach to proving paralel programs correct is presented The steps are 1) model the paralel program, 2) prove partial correctness (proper synchronization), and 3) prove the absence of deadlock, livelock, and infinite loops The parallel program model is based on KeUler's model The main contributions of the paper are techniques for proving the absence of deadlock and livelock A connection is made between Keler's work and Dijkstra's work with serial non-deterministic programs It is shown how a variant function may be used to prove finite termination, even if the variant function is not strictly decreasing, and how finite termination can be used to prove the absence of livelock Handling of the finite delay assumption is also discussed The illustrative examples indude one which occurred in a commercial environment and a classic synchronization problem solved without the aid of special synchronization primitives

Abstract: A system is disclosed for switching a load between two ac sources wherein no degree of synchronization therebetween is required and wherein the switching is accomplished with the use of two electro-mechanical relays each having a three pole, double throw contact arrangement. Furthermore, this load switching is accomplished without the production of any interpower currents between the two sources.

Abstract: The structure of the "parity check" sequence formed on a binary counter has been well studied and is known as a Thue-Morse sequence [1]-[4]. It is shown that this sequence can be used in a simple synchronization scheme that can be engineered with a minimum of hard-ware.

Abstract: In object-oriented languages (e.g., LISP, Simula, and CLU), all (or most) data objects used by a program are implicitly allocated from a free-storage area and are accessed via fixed-size references. The storage for an object is automatically reclaimed (garbage collected) when the object is no longer accessible to the program. This thesis presents the design of a computer system that directly supports an object-oriented machine language. The machine provides a single, large universe of objects shared by multiple processes. The design uses expected future technologies (fast-access secondary storage devices and inexpensive processors) to satisfy the goals of good performance and a simple, modular system organization. Automatic storage reclamation is performed primarily using reference counts. The proposed reference count implementation reduces the time overhead of automatic storage reclamation and allows most reclamation processing to be performed in parallel with normal computation. In addition, the reference count scheme can be used in a multiprocessor configuration without introducing complex synchronization problems. Using a simple transaction model we show that recognizing the transaction histories which are serializable is an NP-complete problem. We therefore introduce several efficiently recognizable subclasses of the class of serializable histories; most of these subclasses correspond to serializability principles existing in the literature and used in practice. We also propose two new principles which subsume all previously known ones. We give necessary and sufficient conditions for a class of histories to be the output of an efficient history scheduler; these conditions imply that there can be no efficient scheduler that outputs all of serializable histories studied above have an efficient scheduler. Finally, we show how our results can be extended to far more general transaction models, to transactions with partly interpreted functions, and to distributed data base systems.

Abstract: Recently we described a variable-frame-rate LPC vocoder designed to transmit good quality speech over 2400 bps fixed-rate noisy channels with bit-error probabilities ranging up to 5% [3]. The basic idea was to lower the data rate by transmitting LPC parameters only when speech characteristics have changed sufficiently since the last transmission, and to employ the resulting bit-rate savings for protecting important transmission data against channel noise. This paper describes our continuing efforts which have concentrated on minimizing loss of synchronization between the receiver and the transmitter. In one approach, we emphasize heavy protection of header, and rapid resynchronization. Alternatively, we apply constraints which guarantee synchronization at a cost of some freedom in the selection of data for transmission. Results from the first approach are presented; results from both methods will be compared at the conference.

Abstract: This paper examines the key issues involved in choosing synchronization techniques applicable to both terrestrial and satellite switching networks. The terrestrial networks considered involve circuit switching, message switching, packet switching, and other integrated voice/data nodal configurations. The satellite networks considered involve time-division multiple access (TDMA) systems and their associated synchronization problems. Peculiar problems associated with satelliteswitched TDMA (SS/TDMA) network synchronization are also addressed. Finally, the issues involved in synchronizing integrated satellite/terrestrial networks are addressed. Emphasis will be placed on assessing the state of the art of current terrestial/satellite synchronization technology and projecting future trends.

Abstract: In a telecommunications network, the use of time division switches which directly operate on Pulse Code Modulated bit streams requires the use of some means for synchronizing the clock rates of such switches. Various methods for achieving synchronization are discussed. Master-slave synchronization has been selected as the most appropriate approach for the Bell System's switched digital network. Some aspects of this approach are considered.

Abstract: Any programming language that supports concurrency needs a synchronization construct with which to express access control for shared resources This thesis examines synchronization constructs from the standpoint of language design for reliable software The criteria a synchronization mechanism must satisfy to support construction of reliable, easily maintainable concurrent software are defined Some of these criteria, such as expressive power, can be defined only with respect to the set of problems the mechanism is expected to handle A definition of the range of problems considered to be synchronization problems is therefore needed Such a definition is provided by describing the possible types of constraints that may be imposed on access to shared resources We then use this taxonomy of synchronization constraints to develop techniques for evaluating how well synchronization constructs meet the criteria discussed These techniques are then applied to three existing synchronization mechanisms: monitors, path expressions, and serializes Evaluations are presented, and the three mechanisms compared