TL;DR: In this article, a method of maintaining synchronization between two independently clocked, stored-program computer processors which are executing the same program simultaneously and are connected in a master-slave relationship is presented.
Abstract: A method of maintaining synchronization between two independently clocked, stored-program computer processors which are executing the same program simultaneously and are connected in a master-slave relationship. There is further provided a method of preventing a failure from disabling both master and slave units. A special function is inserted at selected intervals which delays the master processor until the slave processor catches up. Further, means are provided to automatically detect when a failure occurs. This program alignment and error detection are accomplished by inserting checkpoints at selected intervals at which the redundantly processed results are compared.
TL;DR: Formalization of a well-defined synchronization mechanism can be used to prove that concurrently running processes of a system communicate correctly.
Abstract: This paper appears in the March, 1972, issue of the Communications of the ACM. Its abstract is reproduced below.Formalization of a well-defined synchronization mechanism can be used to prove that concurrently running processes of a system communicate correctly. This is demonstrated for a system consisting of many sending processes which deposit messages in a buffer and many receiving processes which remove messages from that buffer. The formal description makes it very easy to prove that the buffer will neither overflow nor underflow, that senders and receivers will never operate on the same message frame in the buffer nor will they run into a deadlock.
TL;DR: In this article, a data storage and retrieval system capable of performing various arithmetic functions such as adding and subtracting and which includes two principal units is presented, including a console which contains a keyboard for introducing data, a display readout, and various switches to perform the data introduction, storage, retrieval, and some modifications to the data.
Abstract: A data storage and retrieval system capable of performing various arithmetic functions such as adding and subtracting and which includes two principal units. The first of these units is a console which contains a keyboard for introducing data, a display readout, and various switches to perform the data introduction, storage, retrieval, and the various arithmetic functions, as well as certain modifications to the data. The second unit, which forms part of the system, is a central electronics unit which includes a memory section. The memory section includes input/output electronics as well as track selection electronics. The central electronics unit provides for addition and subtraction functions as well as control of the memory section through actuation of the various switches on the console unit. The data which is to be stored in the memory section and which is to be processed via the various arithmetic function is preceded by an identification number which may represent a stock or part number or other logical identification indicia of the stored data. This data is stored randomly in the memory section and discoverable by systematic searching. The central electronics unit includes devices for introducing clock pulses needed in the extraction of data in the memory section. In order to achieve high speed data transfer over substantial cable length, an early clocking mechanism to achieve pre-clock-data synchronization is employed. Information on the various tracks of the memory element is compared with the address or identification number manually introduced into a storage register. In essence, the system operates on the basis of a modified form of associative addressing. An embodiment of the system utilizes a combination of a modified form of associative and direct addressing. Corresponding addresses will enable the comparator to generate an output at a clock pulse time. The system is designed so that more than one console unit may be used with a single central electronics unit. Provision is made to prevent simultaneous change of data at a particular address by two different console units. The system of the present invention may also be operated with either numeric or alpha numeric codes.
TL;DR: In this paper, a blocking synchronization for motor vehicle change-speed transmissions is proposed, in which an axially displaceable shifting sleeve cooperates with synchronizing rings, which are also axially disableable and rotatable within limits.
Abstract: A blocking synchronization for motor vehicle change-speed transmissions in which an axially displaceable shifting sleeve cooperates with synchronizing rings also axially displaceable and rotatable within limits; the synchronizing rings, in turn, cooperate by means of blocking surfaces with the engaging tooth system at the gear whereby the synchronizing rings are centered as well as limited in their axial movability with respect to the shifting sleeve at the gear part carrying the same.
TL;DR: A comparison among three precise t iming centers in the United States has been conducted for more than one year using three different synchronization methods as mentioned in this paper, including cesium beam portable c locks, Loran-C t ransmissions f rom Cape Fear, North Carolina, and Dana, Indiana, and ABC, CBS, and NBC network television broadcasts common to the three t ing centers.
Abstract: A comparison among three precise t iming centers in the United States has been conducted for more than one year using three different synchronization methods. The t iming centers involved were the United States Naval Observatory (USNO) in Washington, D. C . , Newark Air Force Station (NAFS) in Newark, Ohio, and the National Bureau of Standards (NBS) in Boulder, Colorado. The three methods were cesium beam portable c locks; Loran-C t ransmissions f rom Cape Fear , North Carolina, and Dana, Indiana; and ABC, CBS, and NBC network television broadcasts common to the three t iming centers.
TL;DR: In this article, the pseudorandom coded sequence is used to ensure that this situation will be noted and the false outputs ignored, and means are also provided for initially establishing the synchronization between the received and reference sequences and also for automatically synchronizing the sequences if they are out of sync for less than the period between multiplexed pulses.
Abstract: In a time-division multiplexed optical communication system, a coded optical waveform is transmitted with the data sequence. The waveform follows a type of pseudo-random sequence termed an incoherent coded word. At the receiver, the coded and data sequence are demultiplexed into separate channels and combined with an identical reference sequence generated at the receiver. Each combined reference and demultiplexed pulse of the sequences is detected at an associated coincidence detector. The demultiplexing means also presents each pulse of the multiplexed beam to each coincidence detector. If the reference and demultiplexed sequences are out of synchronization, the reference sequence may combine with these unwanted pulses, thereby yielding false outputs from the detectors. The properties of the pseudorandom coded sequence are used to ensure that this situation will be noted and the false outputs ignored. When the demultiplexed and reference sequences are in synchronization, the combined coded synchronization pulses of the demultiplexed and reference sequences are received simultaneously at their associated coincidence detectors in the synchronization channels. The outputs from the detectors are fed to a single photomultiplier-matched filter. The filter is conditioned to generate a significant output only when it receives all of the outputs from the detectors in the synchronization channels simultaneously. If the demultiplexed and reference sequences are out of synchronization, the properties of the pseudorandom coded sequence ensure that not more than one reference and demultiplexed pulse of said coded synchronization sequence is received simultaneously at the matched filter. Under this condition, the filter will generate virtually no output. To ensure that optical pulses of the data sequence do not combine with the synchronization sequence at the receiver, means are provided for excluding all pulses except synchronization pulses from the synchronization channels. Means are also provided for initially establishing the synchronization between the received and reference sequences and also for automatically synchronizing the sequences if they are out of sync for less than the period between multiplexed pulses.
TL;DR: It is shown that by proper selection of Walsh codes, the synchronization requirements can be alleviated considerably and it may be possible to operate the system asynchronously.
Abstract: Walsh functions are potentially applicable to random-access communication provided that requirements for system synchronization and channel linearity are not too severe. This paper investigates the problem of detection of a desired Walsh-code modulated sinusoidal carrier in the presence of other signals for the case when synchronization is not achieved among the users of the system. It is shown that by proper selection of Walsh codes, the synchronization requirements can be alleviated considerably and it may be possible to operate the system asynchronously. The effect of hardlimiting and the problem of transmitting a number of Walsh signals through a power-law device are also considered.
TL;DR: In this article, two extensions to the semaphore operators originally introduced by Dijkstra are described to reduce the number of references, the time spent in critical sections, and the distinct semaphores required for proper synchronization.
Abstract: This paper describes two extensions to the semaphore operators originally introduced by Dijkstra. These extensions can be used to reduce: 1) the number of semaphore references; 2) the time spent in critical sections; and 3) the number of distinct semaphores required for proper synchronization without greatly increasing the time required for semaphore operations. Communicating semaphores may be utilized not only for synchronization but also for message switching, resource allocation from pools and as general queueing mechanisms.
TL;DR: In this article, a motion picture is synchronized with the sound reproduced by a tape recorder by using a converter which is provided with a digital input representing the difference in number of pulses between the accumulated number of synchronization pulses generated respectively by the motion picture projector and the tape recorder.
Abstract: A motion picture is synchronized with the sound reproduced by a tape recorder. The drive motor of the motion picture projector is controlled by a D.A converter which is provided with a digital input representing the difference in number of pulses between the accumulated number of synchronization pulses generated respectively by the motion picture projector and the tape recorder.
TL;DR: In this paper, a transistor arrangement is provided to obtain criteria indicative of the operating condition of the synchronization transmitters, and asynchronous operation of the transmitters is also indicated by the supervision circuit.
Abstract: A circuit to supervise synchronization transmitters to determine if they are functioning properly, and if not, to substitute therefor correctly operating synchronization transmitters. A transistor arrangement is provided to obtain criteria indicative of the operating condition of the synchronization transmitters. A plurality of synchronization transmitters may be supervised to determine the operating conditions thereof with a single supervision circuit. Asynchronous operation of the transmitters is also indicated by the supervision circuit.
TL;DR: A possible means for the external electromagnetic synchronization of an implanted fixed rate cardiac pacemaker is described and can also provide paired-pulse stimulation, coupled stimulation and pacing synchronous with a spontaneous heart rhythm.
Abstract: A possible means for the external electromagnetic synchronization of an implanted fixed rate cardiac pacemaker is described. The method presented can also provide paired-pulse stimulation, coupled stimulation and pacing synchronous with a spontaneous heart rhythm.
TL;DR: In this article, a channel synchronization control circuit for a PCM telecommunication system is described, in which for each group of trunks there is provided a synchronization circuit with data memories for each trunk.
Abstract: A channel synchronization control circuit is disclosed for a PCM telecommunication system in which for each group of trunks there is provided a synchronization circuit with data memories for each trunk. Each message is constituted by a plurality of digits equal to the number of trunks. Received message signals are stored in a buffer memory in which the time modification due to failure of channel synchronization can be corrected. The circuit continuously checks the channel synchronization and continuously applies such corrections as are necessary.
TL;DR: An optical synchronization technique is described for the demultiplexer of a wideband optical data transmission system, in which closely spaced optical pulses of interleaved PCM channels are "space sorted" by a coincidence detection technique using an optical reference waveform generated in the receiver.
Abstract: An optical synchronization technique is described for the demultiplexer of a wideband optical data transmission system. In this system, the closely spaced optical pulses of interleaved PCM channels are "space sorted" by a coincidence detection technique using an optical reference waveform generated in the receiver. For synchronization of the reference waveform with a spatial waveform produced by the received laser beam in the demultiplexer, a number of pulses on these two optical waveforms are coded with a pseudo-random sequence. Acquisition of the coded waveforms for synchronization is indicated in an optical matched filter. For automatic tracking, a synchronization error-control circuit is added.