Abstract: A RISC architecture with vector operands proves to be useful as a general purpose architecture. It provides a .powerful instruction set which can be implemented in a high performance CPU. Even the highest performance implementation is comparatively small and inexpensive, and lower performance implementations are comparable with present or contemplated 32 bit microprocessors. The utility of such CPU's in crossbar multiprocessors is mentioned in [I], and implicit in [2]. In [I] it is suggested that an IEEE standard instruction set be established.