TL;DR: A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented and a technique to eliminate the front-end sample hold, thereby reducing power consumption is presented.
Abstract: A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB.
TL;DR: In this article, a methodology for the estimation of sample processing and sub-sampling performance based on the comparison of the global method experimental dispersion of results with the uncertainty estimated from developed models for the subsequent analytical steps is presented.
TL;DR: In this paper, a block divider (202) divides the block into subblocks (SB's) of KxL pixels and then classifies the SB's into A-group SB's and B-groupSB's in accordance with the rule that all SB's in a same group be diagonally adjacent to each other.
Abstract: In an apparatus (300) for performing motion estimation (ME) on a block of NxM pixels in a current frame based on a predetermined reference frame (RF), a block divider (202) divides the block into subblocks (SB's) of KxL pixels and then classifies the SB's into A-group SB's and B-group SB's in accordance with the rule that all of the SB's in a same group be diagonally adjacent to each other. A first and a second decision circuits (204, 206) decide pixels satisfying a first and a second predetermined conditions among the pixels in the ASB's as A-group representative pixels (ARP's) and in the BSB's as B-group representative pixels (BRP's), respectively, wherein the first predetermined condition is different from the second predetermined condition. A sample block generator (208) combines the ARP's with the BRP's to generate a sample block. And then, RF sub-sampling circuit (210) generates a sample RF (SRF) by sub-sampling the predermined RF in accordance with the same sub-sampling method described above. A best matching candidate block (CB) detector (220), based on the sample block and the SRF, detects a CB having a smallest error value to the sample block among CB's within the SRF as a best matching CB (BMCB) by using a predetermined block matching method. And a motion vector (MV) generator (222) generates a MV representing a displacement between the sample block and the BMCB.
TL;DR: A quadrature sub-sampling direct conversion mixer capable of sampling two or more bands concurrently using a single sampling frequency is presented and the proposed circuit is analyzed in detail and the results are validated using Spectre RF simulations for a 0.18μm CMOS process.
Abstract: A quadrature sub-sampling direct conversion mixer capable of sampling two or more bands concurrently using a single sampling frequency is presented. The implementation of the mixer to sample a band in quadrature and downconvert it to baseband is discussed and it is shown how this idea could be extended to sample in quadrature two or more bands concurrently. The proposed circuit is analyzed in detail and the results are validated using Spectre RF simulations for a 0.18μm CMOS process.
TL;DR: In this article, a block containing the notice picture element and the peripheral picture elements of image data for learning is constituted, and a value subtracting a reference value 'base' of the block is divided by a dynamic range DR at a normalizing circuit 20.
Abstract: PURPOSE:To reduce the capacity of a memory and the scale of a hardware when generating an estimated value and to improve the accuracy of the generated estimated value. CONSTITUTION:A block containing the notice picture element and the peripheral picture elements of image data for learning is constituted. A value subtracting a reference value 'base' of the block is divided by a dynamic range DR at a normalizing circuit 20. A frequency memory 16 and a data memory 17 are address-designated by a class code (c). An integral representative value is generated from a multiplier 22, added with the present normalized output and divided by an integral frequency at a divider 23. The representative value from the divider 23 is written in the data memory 17. The data, which dynamic range DR is smaller than a threshold value, is excluded from a learning target by a control signal Sc. The representative value as the result of learning is used for interpolating a sub sampling signal.