STD Bus

Abstract: A time-division multiplexed, data communications system allowing multiple user devices, including super computer buses configured in a local network, and other existing network hierarchies to exchange digital data over extended distances at speeds heretofore unattainable. The system includes a plurality of intelligent nodes, termed "DATApipe™ adapters", which are coupled to a fiber optic bus. The DATApipe adapters function as interface devices between the fiber optic bus and the I/O processors which are used to couple the user devices and networks to the DATApipe adapters.

Abstract: A system, method, and computer readable medium adapted to provide software and hardware partitioning for multi-standard video compression and decompression comprises a master-slave bus, a peer-to-peer bus, and an inter-processor communications bus, a prediction engine, a filter engine, and a transform engine, and a video encode control processor, and a video decode control processor adapted to utilize the master-slave bus to interact with the video hardware engines for control flow processing, the peer-to-peer bus for data flow processing, and the inter-processor communications bus for inter-processor communications, and a system data bus adapted to permit data exchange between system resources, the busses, the engines, and the processors.

Abstract: A directional comparison bus protection unit (DCBPU) can provide a high speed bus fault clearing in the IEC61850 process-bus environment. This technique is based on superimposed fault direction for each circuit connected to the protected bus. In this paper, the implementation and testing of a superimposed directional comparison technique for bus protection based on an IEC61850 process bus is investigated. Design, hardware implementation, and related issues of DCBPU are described. A unique test setup is proposed and developed for testing DCBPU, including merging unit simulator, traffic generator, prototype DCBPU, and Ethernet switches to simulate the real IEC 61850-based substation automation process bus. Test results are reported.

Abstract: A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The 3-D graphics accelerator includes a plurality of direct data channels or point-to-point buses, collectively referred to as the CF bus, which connect the command preprocessor to each of the plurality of floating point processors. The 3-D graphics accelerator also includes a plurality of direct data channels or point-to-point buses, collectively referred to as the FD bus, which connect the plurality of floating point processors to each of the draw processors. The system of the present invention also implements a bus from the command preprocessor directly to the draw processors, referred to as the CD bus, which uses portions of the above direct data channels. The CD bus shares or "borrows" the data lines from the CF bus and the FD bus and uses the floating point processors as buffer chips. This allows implementation of a "logical" bus while using existing bus lines.