Spinlock

Abstract: Closely related processing threads within a process in a multiprocessor system are collected into thread groups which are globally scheduled as a group based on the thread group structure's priority and scheduling parameters. The thread group structure maintains collective timeslice and CPU accounting for all threads in the group. Within each thread group, each individual thread has a local scheduling priority for scheduling among the threads in its group. The system utilizes a hierarchy of processing levels and run queues to facilitate affining thread groups with processors or groups of processors when possible. The system will tend to balance out the workload among system processors and will migrate threads groups up and down through processing levels to increase cache hits and overall performance. The system is periodically reset to avoid long term unbalanced operation conditions.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor (110) and thread switch logic (400) The multithreaded processor (110) is capable of switching between two or more threads of instructions which can be independently executed Each thread has a corresponding state in a thread state register (440) depending on its execution status The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread switch can occur Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time Thread switch logic also has a forward progress count register (420) to prevent repetitive unproductive thread switching between threads in the multithreaded processor Thread switch logic also is responsive to a thread switch manager (460) capable of changing the priority of the different threads and thus superseding thread switch events

Abstract: A processor (300) includes a thread switching control logic (610) that performs a fast thread-switching operation in response to an L1 cache miss stall The fast thread-switching operation implements one or more of several thread-switching methods A first thread-switching operation is 'oblivious' thread-switching for every N cycle in which the individual flip-flops locally determine a thread-switch without notification of stalling The oblivious technique avoids usage of an extra global interconnection between threads for thread selection A second thread-switching operation is 'semi-oblivious' thread-switching for use with an existing 'pipeline stall' signal (if any) The pipeline stall signal operates in two capacities, first as a notification of a pipeline stall, and second as a thread select signal between threads so that, again, usage of an extra global interconnection between threads for thread selection is avoided A third thread-switching operation is an 'intelligent global scheduler' thread-switching in which a thread switch decision is based on a plurality of signals including: (1) and L1 data cache miss stall signal, (2) an instruction buffer empty signal, (3) an L2 cache miss signal, (4) a thread priority signal, (5) a thread timer signal, (6) an interrupt signal, or other sources of triggering In some embodiments, the thread select signal is broadcast as fast as possible, similar to a clock tree distribution In some systems, a processor derives a thread select signal that is applied to the flip-flops by overloading a scan enable (SE) signal of a scannable flip-flop

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.