Shmoo plot

Abstract: A method of operating an integrated circuit (IC) tester is disclosed in which an IC is repeatedly tested with respect to a limited number of combinations of values of two variable IC operating parameters (X and Y) to determine the boundary of a two-dimensional range of combinations of values of the X and Y parameters for which the IC passes a test. After finding a combination of X and Y parameter values on the boundary, each combination of parameter values to be tested thereafter is selected by altering either the X or Y parameter value, with the decision based on whether the IC passed the last test and on the manner in which a last tested combination of X and Y parameter values was selected.

Abstract: In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the impedance-calibration circuit and to minimize CIO in the coded output driver. With these methods, a data rate of 3 Gb/s/pin is achieved and the shmoo plot. The micrograph of the output driver and impedance calibration circuit, which is implemented in a 66 nm 512 Mb GDDR3 SDRAM.

Abstract: Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

Abstract: An IC test device and method are provided which can display the results of a SHMOO plot accurately by performing decisions only for the necessary portions thereof, thus shortening the time required for performing data acquisition. A test point separation section groups the test points within the testing range for the SHMOO plot into blocks. A control section performs pass/fail decisions via a testing section for test points at the vertices of the blocks, and, from the patterns of decision results, picks out those blocks for which the test results for adjacent vertices are different, and picks out as complete testing blocks for which is to be tested at all the test points included in them, those blocks which have in common an edge region which includes vertices for which the test results differ. The testing section performs pass/fail decisions for all the test points within the complete testing blocks.