Shift register

Abstract: An all-metallic submicrometer device is demonstrated experimentally at room temperature that performs logical NOT operations on magnetic logic signals. When this two-terminal ferromagnetic structure is incorporated into a magnetic feedback loop, the junction performs a frequency division operation on an applied oscillating magnetic field. Up to 11 of these junctions are then directly linked together to create a magnetic shift register.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

Abstract: Shift registers have been used to generate sequences of 0’s and 1’s for over thirty years. A wide variety of applications has been made of these sequences. Principally, communications have made use of the sequences generated.One particular class of shift register sequences for which applications exist is the full length nonlinear shift register sequences. These sequences are periodic and of length $2^n $ and all $2^n $ different binary n-tuples appear exactly one time in a periodic portion of the sequence. In this paper we discuss various algorithms which have been suggested for generating these sequences.