Abstract: A class of iterative integer division algorithms is presented based on look-up table and Taylor-series approximations to the reciprocal. The algorithm iterates by using the reciprocal to find an approximate quotient and then subtracting the quotient multiplied by the divisor from the dividend to find a remaining dividend. Fast implementations can produce an average of either 14 or 27 b per iteration, depending on whether the basic or advanced version of this method is implemented. Detailed analyses are presented to support the claimed accuracy per iteration. Speed estimates using state-of-the-art ECL components show that this method is faster than the Newton-Raphson technique and can produce 53-b quotients of 53-b numbers in about 25 ns using the basic method and 21 ns using the advanced method. In addition, these methods naturally produce an exact remainder, which is very useful for implementing precise rounding specifications. >

Abstract: In an arithmetic processor, second data are subtracted from first data to derive a first overflow signal. The sum of the second data and "1" is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and second data derived is detected from the derived overflow signals.

Abstract: A method for tracking errors in a system of numerical formulas. It uses confidence intervals and special encodings, and is suitable for use in an interactive computer program. Maximum efficiency and accuracy are attained by using directed rounding and compiling into native code.

Abstract: In implementations of operations based on digit-recurrence algorithms such as division, left-to-right multiplication and square root, the result is obtained in digit-serial form, from most significant digit to least significant. To reduce the complexity of the result-digit selection and allow the use of redundant addition, the result-digit has values from a signed-digit set. As a consequence, the result has to be converted to conventional representation, which can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder. The authors describe three ways to modify this conversion process so that the result is rounded. The resulting operation is fast because no carry-propagate addition is needed. The schemes described apply also to online arithmetic operations. >

Abstract: Depth maps are frequently analyzed as if, to an adequate approximation, the errors are normally, identically, and independently distributed. This noise model does not consider at least two types of anomalies encountered in sampling: A few large deviations in the data, often thought of as outliers; and a uniformly distributed error component arising from rounding and quantization. The theory of robust statistics formally addresses these problems and is efficiently used in a robust sequential estimator (RSE) of our own design. The specific implementation was based on a t-distribution error model, and this work extends this concept to several well known M-estimators. We evaluate the performance of these estimators under different noise conditions and highlight the effects of tuning constants and the necessity of simultaneous scale and parameter estimation.

Abstract: In new, iterative continuum-based optimality criteria (COC) methods, the strain in the adjoint structure becomes non-unique if the number of active local constraints is greater than the number of design variables for an element. This brief note discusses the use of smooth envelope functions (SEFs) in overcoming economically computational problems caused by the above non-uniqueness.

Abstract: Apparatus for converting to a single precision or double precision number an extended precision floating point number comprised of a sign field, an exponent field and a mantissa field. A sticky generation logic connected to the mantissa bus calculates rounding bits for single and double precision and places the rounding information at a sticky output. Overflow and underflow detection logic connected to the exponent bus detects exponent overflow and underflow and generates an overflow output signal. Rounding and conversion control logic connected to the sticky output utilizes the type of conversion that has been specified and the rounding information at the sticky output for producing conversion controls at a control output and a conversion type signal output. A positional incrementer connected to the exponent bus, to the mantissa bus, and to the rounding and conversion control logic places on an incrementer output, the incremented number in response to the conversion type signal output of the rounding and conversion control logic. A conversion mux is connected to the exponent bus, to the mantissa bus, to the output of the positional incrementer and to the control output of the rounding and conversion control logic. In response to the control output of the rounding and conversion control logic means, the conversion mux places either the exponent bus and the mantissa bus, or the output of the positional incrementer means on a conversion output of the conversion mux.

Abstract: An expert system which combines operators' dispatching rules and the integer linear programming (LP) routine is designed for voltage control of the Taiwan Power Company. To reach the control actions at one time and to avoid the need of rounding off the control actions for capacitors/inductors and transformer taps, the efficient integer LP routine is developed using the branch-and-bound algorithm. The operators' heuristic rules and sensitivity factors are used to reduce the number of variables and constraints in the integer LP formulation in order to reduce the computational time and to make the approach feasible in real-time situations. The expert system was applied to correct abnormal voltages during emergency conditions. It was found that the proposed expert system is a valuable aid to system operators for voltage control. >

Abstract: This paper is concerned with how standard estimation procedures perform in terms of eficiency for non-normal rounded data. Previous research has shown that the loss in eficiency due to rounding normal data is small. However, evidence from the non-normal distribution considered in this paper suggests, if rounding is coarse or the distribution is very skewed the loss in efficiency due to rounding can be considerable.

Abstract: PURPOSE:To reduce an overshoot and remaining vibration and to enable great noise reduction by rounding the time waveform of an applied voltage at the time of switching to an opposite polarity from a zero voltage along an exponential function and specifying the time constant of this rounding. CONSTITUTION:Capacitors C1 - C4 are connected to the terminals of resistances R2, R6, R12, and R18, connected to the bases of transistors TR1 - TR4, on the opposite side from the TRs 1 - 4. The other-terminal sides of those capacitors C1 - C4 are grounded and resistances R21 and R22 are connected to the collectors of TRs 7 and 8. When a TTL signal S1 is switched from a low level to a high level, the collector current of a TR 5 varies while delayed by the time constant determined by the resistance value of a resistance R3 and the electrostatic capacity of the capacitor C1. At this time, the applied voltage of stator winding is rounded with R/C according to the exponential function by using the capacitance C of the capacitor C1 and the resistance value R of the resistance R3. In this case, the time constant of the rounding should be >= (1/4) time as large as the characteristic period of a motor rotation system.

Abstract: Abstract In demographic longitudinal studies, time measurements in the data are mostly reported in a rounded form: a time unit is fixed, typically a month or a year, and then the interval (of unit length) during which the event in question occurred is reported. Such rounding does cause some problems, however. For example, it may result in a considerable number of ties, and the computer-time requirement can be excessive for methods such as Cox’s proportional-hazards regression. A slightly different problem arises in using the Poisson regression technique with piecewise constant-baseline hazards, which requires the estimation of exposure in the various groups. To do this, the rounded time measurements are conventionally modified by applying ‘actuarial methods’, thus introducing an element of spurious accuracy into the data. For example, if the time-interval is a month, a single event is dated to the fifteenth day, and if there are two events, one is dated to the tenth and the other to the twentieth day of the month. If the time intervals are short, these somewhat ad hoc modifications of the essentially discrete data, which are required in order to apply a continuous time-method, appear rather harmless, since the differences between the true, recorded, and modified time measurements are small. However, ‘spurious accuracy’ is somewhat awkward, and it is natural to look for alternatives.

Abstract: In this paper, we show how word rounding techniques can be efficiently used to reduce/eliminate the guard band in systolic Inner Product Array (IPA) circuits. This results in a significant improvement in circuit throughput rate. By incorporating a shift-truncation module either in the main array cells or in the accumulator cells, two different versions of an Automatic-Rounding IPA can be produced--the unidirectional ARIPA circuit and the orthogonal ARIPA circuit. It is shown that the proposed method requires considerably less hardware and has a higher degree of regularity when compared with techniques previously proposed. Maximum system word length reduction can be achieved with the modified unidirectional ARIPA circuit at a slight increase in overall circuit complexity. This allows maximum performance to be achieved.

Abstract: The Θ-algorithm is an extrapolation algorithm which can be very useful in accelerating some slowly convergent sequences. Like the other acceleration algorithms, the Θ-algorithm is quite sensitive to the propagation of rounding errors due to cancellation in the difference between two almost equal quantities. In order to (partially) avoid this drawback, particular rules are given. They have to be used, instead of the usual rules of the algorithm, when two adjacent quantities in a column are nearly equal. Numerical examples show that these rules can improve the numerical stability of the algorithm in some cases while, in other cases, the improvement is non-existent.

Abstract: A method for deriving the distribution of relative round off error in addition of two binary floating-point numbers is introduced. The distribution is needed in the calculation of variance of the relative roundoff error in floating-point addition. The resulting distribution depends on the statistics of the addends and the rounding strategy chosen. As an example, the distribution is derived for the addition of two uncorrelated numbers from Gaussian distribution. The result was verified by simulation. >

Abstract: PURPOSE: To maintain picture quality by eliminating picture element jump in an output picture element by deciding the coordinate value of the output picture element as the coordinate value of a picture element nearest to the coordinate value after coordinate transformation. CONSTITUTION: A level interpolation circuit 7, a write control circuit 8, and image memory 9 are connected to image memory 1 in this order. Also, the output of a rounding circuit 4 is inputted to the write control circuit 8. An input image is stored in the image memory 1 in the order of the scan. Data in the image memory 1 is referred to when an interpolation arithmetic operation is performed. A coordinate value generation circuit 2 generates the coordinate value at an interval less than one picture element interval to write a coordinate transformation result on all the picture elements in an output image when an input image is coordinate-transformed sequentially in the order of the input. A coordinate value transformation circuit 3 transforms the coordinate value generated by the coordinate generation circuit 2 to decide the output picture element after the coordinate transformation. The rounding circuit 4 decides the output picture element by rounding the coordinate value transformed by the coordinate value transformation circuit 3 to integer. COPYRIGHT: (C)1994,JPO&Japio

Abstract: A new procedure is proposed for the calculation of bounds for simple eigenvalues of a real symmetric parameter-dependent matrix. By the use of interval arithmetic, the bounds are secured against rounding errors; thus, the eigenvalues are proved rigorously to have multiplicity equal to one.

Abstract: The first-order two-dimensional direct-form digital filter with magnitude truncation is known to be free from limit cycles for a limited range of allowed filter coefficients. In this correspondence, the quantization technique of controlled rounding is used to extend the region of filter coefficients for which suppression of limit cycles can be proved. With controlled rounding a signal is quantized in the direction of a control signal, which is formed by an integer combination of preceding signal values. The absence of limit cycles is proved with a properly chosen Lyapunov function. >

Abstract: It is shown that floating point realizations of linearly stable systems can exhibit four fundamental types of free responses. The effects of various floating point arithmetic reformatting schemes on the convergence of autoregressive difference equations are addressed. Truncation and rounding quantization schemes as well as double and single length product mantissa schemes are analyzed and compared. >

Abstract: PURPOSE:To improve operating speed by constituting a multiplier for the mantissa part of a signed binary adder tree and a subtractor and finding out the total logical sum of cut-off bits from the output of the signed binary adder CONSTITUTION:The exponential parts E1, E2 of a floating decimal point segmented in the preprocessing stage are mutually added by an exponential part adder 1 The mantissa parts M1, M2 consisting of (n) bits in the floating decimal point are multiplied by each other by a multiplier 2 The total OR H of outputs D, F respectively corresponding to about lower (n) bits of each of the outputs B, C of the signed binary adder tree 21 is found out by an OR circuit 3 A rounding digit positioning device 4 outputs the output I of the floating decimal point multiplier based upon the output A of the adder 1 and the upper bits G of the output of the multiplier 2 by using the total OR H as a control signal Since total delay time = preprocessing + multiplication + rounding digit positioning is formed, the operation time can be shortened only by the calculation time of the total OR

Abstract: PURPOSE:To simplify a system and to execute the rounding deformation of a three-dimensional shape with a small data amount by preparing a loop by repeatedly tracing from a rigid line to an apex and from the apex to the rigid line. CONSTITUTION:When executing the rounding processing of the three-dimensional shape, the history of the rounding deformation processing is added to the constitutive element of a shape to be newly generated as a number corresponding to the accumulation of the rounding deformation processings and further, only the changed part of a shape data is preserved. In the backing processing of the rounding deformation, the preceding shape is reproduced by deleting the data added in the latest rounding processing, restoring data preserved by the rounding processing and arranging those data. Thus, the backing processing of the rounding deformation can be executed while preventing the overlapped increase of the data amount and further without separately managing the history data of the rounding deformation.

Abstract: PURPOSE:To provide an arithmetic device which can operate the floating point data in which the number of processing steps necessary to obtain the mantissa part of the sum, difference and product of the floating point data rounded by the designated rounding mode and the rounding accuracy is small and the hardware is little. CONSTITUTION:A rounding value preparing circuit 106 prepares the data to make the rounding bit into 1 and adds them to an adder 107 together with two input data. A rounding correcting repeating control circuit 109 inverts the lower-most bit of the output of an LRI shifter 108 and instructs to insert the step to perform the addition for the rounding again. Then, the operation and the rounding of the mantissa can be simultaneously performed by the same adder and the number of the processing steps can be decreased without increasing the hardware.

Abstract: We commonly wish to solve a mathematical problem using a mixture of analytical and numerical techniques. An effective approach is to use a computer algebra system to perform the analytical stage (solution of simultaneous equations, substitution of variables, determination of higher derivatives and so on) and then to use a standard numerical analysis package for the numerical stage (solution of differential equations, fitting to experimental data and so on). Numerical analysis packages are invariably written in languages such as FORTRAN and Pascal, with a rather different input syntax to that of the computer algebra system. To achieve an interface it is necessary for the results from the computer algebra system to be output in a suitable form—FORTRAN expressions for example. Most computer algebra systems now provide fairly sophisticated packages to do this, for example REDUCE's GENTRAN package [Hearn, 1987; Gates, 1987]). There is a problem with this approach in that the computer algebra system may generate massive expressions (we have a practical example of 4000 terms in 20 variables). On evaluation with specific values in floating point by the numerical analysis package such expressions are prone to serious rounding, overflow and underflow errors. Work is in progress elsewhere to allow expressions to be evaluated minimising such errors. However we demonstrate an alternative approach, where we get the computer algebra system to evaluate the expressions analytically for the numerical analysis package as and when they are needed.

Abstract: The authors investigate the effects of finite wordlength on the performance of QMF (quadrature mirror filter) banks implemented with fixed-point arithmetic. A statistical model for roundoff errors is used to predict the output roundoff noise in each subband. The amplitudes of the parasitic oscillations which are due to a DC component in each subband are predicted with the same model. For two's complement arithmetic, the authors discuss the effects of truncation and rounding, and present analysis results. A general framework for analyzing different splitting schemes is given. The enhancement of roundoff noise for low frequencies is obvious. It is pointed out that parasitic frequency components can be avoided if two's complement rounding is used, while roundoff noise can only be reduced by increasing the wordlength. >

Abstract: PURPOSE:To attain a rounding calculation with one instruction so as to make the rounding calculation at a high speed by providing a decoding means, selective means, and arithmetic logic computing element. CONSTITUTION:This circuit is provided with a 1st input signal 7 expressed by the complement of 2 and a decoding means 3 generating two kinds of the decoding output signals based on a 2nd input signal 2 which designates the rounding position of the input signal 7 and selective means 6 for which when the most significant bit of the 1st signal 7 is '0', a first decoding output signal is selected and when the most significant bit is '1', a second decoding output signal is selected and on arithmetic logic computing element 8 which inputs the 1st input signal 7 and the output signal of the selective means 6 and makes addition. Thus, positive-negative symmetrical zero-out rounding can be performed to an arbitrary rounding position.