Abstract: We present algorithms for accurately converting floating-point numbers to decimal representation. The key idea is to carry along with the computation an explicit representation of the required rounding accuracy.We begin with the simpler problem of converting fixed-point fractions. A modification of the well-known algorithm for radix-conversion of fixed-point fractions by multiplication explicitly determines when to terminate the conversion process; a variable number of digits are produced. The algorithm has these properties: No information is lost; the original fraction can be recovered from the output by rounding.No “garbage digits” are produced.The output is correctly rounded.It is never necessary to propagate carries on rounding.We then derive two algorithms for free-formal output of floating-point numbers. The first simply scales the given floating-point number to an appropriate fractional range and then applies the algorithm for fractions. This is quite fast and simple to code but has inaccuracies stemming from round-off errors and oversimplification. The second algorithm guarantees mathematical accuracy by using multiple-precision integer arithmetic and handling special cases. Both algorithms produce no more digits than necessary (intuitively, the “1.3 prints as 1.2999999” problem does not occur).Finally, we modify the free-format conversion algorithm for use in fixed-format applications. Information may be lost if the fixed format provides too few digit positions, but the output is always correctly rounded. On the other hand, no “garbage digits” are ever produced, even if the fixed format specifies too many digit positions (intuitively, the “4/3 prints as 1.333333328366279602” problem does not occur).

Abstract: A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

Abstract: The author considers the characteristics of the error resulting when a continuous amplitude signal x/sub n/ is quantized and then multiplied by a constant multiplier a under fixed-point roundoff arithmetic. It is shown that the overall error of such an operation can be decomposed into two terms: one being a scaled version of the error due to the quantization of x/sub n/ and the other due to rounding off the product aQ(x/sub n/). Exact first- and second-order moments are derived for the quantization error, the roundoff error, and the overall error as a function of the multiplier a and the distribution of x/sub n/. Sufficient conditions are given for the quantization error and the roundoff error to be individually uniformly distributed and white up to the first- and second-order moments, and also for them to be mutually uncorrelated. It is also shown that regardless of the probability distribution of the input signal x/sub n/, it is always possible to add a suitable dither signal to the input of the system so that both the quantization error and the roundoff error are uniformly distributed, white, and mutually uncorrelated. For Gaussian inputs, the sufficient conditions given are not satisfied. >

Abstract: Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.

Abstract: A processor has an exception detector for detecting occurrence of Overflow und Underflow exceptions in floating-point data subjected to a rounding operation, said exception detector comprising first detection means for detecting whether the rounding operation to be executed is a rounding operation by raising or a rounding operation by truncating, means for unconditionally performing the rounding operation by raising on a mantissa part of said floating-point data to provide a modified mantissa part, second detection means for detecting a number of an exponent part of said floating-point data, and third detection means, responsive to detection outputs of said first and second detection means and overflow data of said modified mantissa part, for detecting whether or not Overflow or Underflow exception occurs in said floating-point data subjected to the rounding operation.

Abstract: A systematic derivation of a radix-4 square-root algorithm using redundant residual and result is presented. Unlike other similar schemes it does not use a table lookup or PLA for the initial step, resulting in a simpler implementation without any time penalty. The scheme can be integrated with division and incorporates an on-the-fly conversion and rounding of the result, thus eliminating a carry-propagate step to obtain the final result. The result-digit selection uses 3 bits of the result and 7 bits of the estimate of the residual. >

Abstract: Controlled rounding is a procedure that perturbs tabular data collected from respondents in such a way as to preserve the anonymity of the respondents while maintaining the integrity of the data. The three-dimensional controlled rounding problem is NP-complete. This paper describes a binary tree search algorithm for solving three-dimensional problems based on linear programming techniques. Computational results obtained from tests with over 31,000 randomly generated tables and 292 real-life tables have shown that this algorithm can effectively find controlled roundings when they exist or determine that no solution exists. The computational results also demonstrate that the running time of the search algorithm can be cut in half by using a heuristic for initializing the simplex basis for the linear programming problems.

Abstract: In a recursive digital filter the need for applying rounding/truncation and overflow corrections to the signal (data) at appropriate locations causes the filter behaviour to differ in a more or less noticeable way from the desired one. The filter is said to be the more robust the less such differences are pronounced. For assessing robustness, a list of specific effects are proposed which can individually be tested. If the filter behaves properly with respect to all these tests it can be expected to behave properly also in any of the situations it will encounter during its operation. The possibility of guaranteeing robustness is discussed.

Abstract: A standard technique in solid modeling is to represent planes (or lines) by explicit equations and to represent vertices and edges implicitly by means of combinatorial information. Numerical problems that arise from using floating-point arithmetic to implement operations on solids can be avoided by using exact arithmetic. Since the execution time of exact arithmetic operators increases with the number of bits required to represent the operands, it is important to avoid increasing the number of bits required to represent the plane (or line) equation coefficients. Set operations on solids do not increase the number of bits required. However, rotating a solid greatly increases the number of bits required, thus adversely affecting efficiency. One proposed solution to this problem is to round the coefficients of each plane (or line) equation without altering the combinatorial information. We show that such rounding is NP-complete.

Abstract: A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalize circuit (34a) and a round circuit (34b), and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.

Abstract: Controlled rounding is a procedure whereby tabular data gathered from respondents is perturbed in such a way as to preserve the anonymity of the respondents while maintaining the integrity of the data. This paper describes an algorithm for solving three-dimensional controlled rounding problems which is based on simulated annealing, linear programming, and binary search procedures. Numerical results obtained from processing 32,500 randomly generated tables and 292 real-life tables have demonstrated that this algorithm can efficiently find controlled roundings, provided they exist. The algorithm is significantly faster than any previously known solution procedure for this class of problems. INFORMS Journal on Computing, ISSN 1091-9856, was published as ORSA Journal on Computing from 1989 to 1995 under ISSN 0899-1499.

Abstract: A versatile floating point adder which performs high speed floating point addition or subtraction on operands supplied in a signed magnitude format includes separate exponent and mantissa data paths for processing the exponent fields and mantissa fields of the floating point binary numbers to be added or subtracted. The exponent data path computes the absolute difference between the exponents of the floating point numbers, passes the large exponent, and adjusts the large exponent by an amount needed to normalize the mantissa and to reflect an overflow in the mantissa addition/substration and mantissa rounding operations. The mantissa data path denormalizes one of the input mantissas, adds the two mantissas after the denormalization operation, post-normalizes the resulting mantissa, and rounds the mantissa to the correct precision.

Abstract: Controlled rounding is a procedure that perturbs tabular data collected from respondents in such a way as to preserve the anonymity of the respondents while maintaining the integrity of the data. Controlled rounding techniques are regularly used by the United States Bureau of the Census and its counterparts in other countries. This paper discusses the complexity of the three-dimensional controlled rounding problem. In particular, the three-dimensional, zero-restricted controlled rounding problem is shown to be NP-complete. As zero-restricted controlled roundings may fail to exist, various relaxations of this basic rounding problem have been defined. The paper introduces a sequence of such relaxations and proceeds to address the existence of solutions and complexity issues for the relaxed problems.

Abstract: In a method of drawing parametric curve on second-dimensional coordinate having discrete coordinate values, when rounding respective points on curve obtained by equal division in adjacent points, the nearest lattice point is not selected, but instead, if the incline value of this point is more than 1, an adjacent point containing integral X-coordinate is approximately computed, whereas if the incline value of this point is less than 1, an adjacent point containing integral Y-coordinate is approximately computed. Since specific lattice points nearest to the computed points are selected, smooth curve can be drawn without causing redundant point to occur at all. When executing linear interpolation, interpolation is executed by means of a straight line passing through the not-yet-rounded point without using such a line passing through the already rounded point. As a result, satisfactory linear interpolation very close to true curve can be achieved constantly.

Abstract: A multiple selector logic circuit for selecting divisor multiples in 2-bit, non-restoring divide sequences, which provides a proper and accurate quotient result and remainder, and which produces rounding and indication of exact or inexact result in conformance with ANSI/IEEE Standard 754-1985; the multiple selector logic circuit incorporates semiconductor circuits including a multiplier table having a particular matrix of multipliers which meet the standard.

Abstract: Consideration of bounds, discontinuities and the integrality of decision variables is often helpful for responding to many practical requirements. Using the case of quantity discounting as an example, it is shown why the above considerations add realism to a model, and how they may be incorporated in the solution procedure. The bounds on the order quantity are fulfilled by establishing suitable stopping rules, while gaps in order quantities are resolved by modifying the input data. As for integrality, a result is established which shows that the feasible points for the integer optimum can be obtained by suitably rounding those for the continuous optimum. A comprehensive algorithm containing these features is proposed, and analytical proofs of the results are included.

Abstract: Abstract The level-index number system represents numbers in a computer by their repeated logarithms. Its chief advantage is closure in finite¬ precision arithmetic, thereby eradicating the problems of overflow and underflow. This talk indicates how a Wilkinson-type running error analysis can be carried out in the new system.

Abstract: In a previously published study, the effects of rounding on the significance and power of four test statistics were considered when the parent population was normal. Here we investigate how these tests will perform for rounded non-normal data. Guidelines are given on how the degree of precision recommended for normal populations can be applied when the population is non-normal.

Abstract: An approximate solution Ya of a function F with respect to a given value X is derived by referring to a relation Y=F(X) at an accuracy at which an error between the approximate solution Ya and an infinitely precise solution Y is smaller than a weight of a digit in a place lower than a lowest place of significant digits for a final solution by two places. The approximate solution Ya is rounded to an interim solution Yr equal to one of possible interim solutions which is closest to the approximate solution Ya. A value Xr is derived from the interim solution Yr and an inverse function F -1 by referring to a relation Xr=F -1 (Yr). A sticky digit S is set to 0, 1, or -1 in response to the relation between the magnitudes of the values X and Xr and other information. The sticky digit S is added to a place immediately lower than a lowest place of the interim solution Yr. A result of this addition is rounded in a designated rounding mode to obtain the final solution.

Abstract: Due to their ever increasing complexity, it is becoming difficult to assure that hardware systems will not malfunction because of design errors. Hardware verification involves using theoremproving techniques to verify that the design of a system satisfies its specification. This paper describes work in progress on verifying a floating-point coprocessor based on the MC68881/82, with respect to the IEEE standard floating-point arithmetic (ANSIIEEE Std 754-1985). A complete formalization of the IEEE floating-point standard using the HOL (Higher-Order-Logic) specification and verification system developed at Cambridge University is presented. The specification of floating-point numbers, floating-point arithmetic functions, rounding schemes and postnormalization are described. In order for the specification to be adaptable to different implementations, several model parameters are used in specifying all the functions. The floating-point coprocessor is specified as a hierarchy of interpreters. The communication with the CPU is modeled as standard interprocessor communication. A technique for verifying hierarchies of communicating hardware interpreters is described.

Abstract: First order phase transitions are rounded in solids of finite size. It is shown here that the above rounding is monitored by the correlation length ξL of the finite system, or equivalently by the so-called mass gap for the quantum Hamiltonian version of the model. Scaling with size is studied as a function of variable boundary conditions for the cylinder geometry (infinite strips with finite width), and a striking crossover is found in the mass gap behavior when the coupling g along the boundary becomes anti-periodic. For g>0, the rounding is exponential with size and an accurate determination of the spontaneous magnetization (order parameter) of the infinite system is obtained from numerical extrapolations.

Abstract: PURPOSE:To increase arithmetic processing speed for extraction of the square root by supplying the output of a bit inverting circuit to a rounding circuit via a multiplexer only in a partial arithmetic process for extraction of the square root and performing a right shift by one bit after addition of 1 to the minimum digit. CONSTITUTION:A multiplexer 8 supplies the output of a bit inverting circuit 7 to a rounding circuit 6 only in a partial arithmetic process for extraction of the square root. The output of the circuit 7 receives 1 at its minimum digit and is shifted to the right by one bit in the circuit 6. Otherwise the output of a right shift circuit 5 is supplied directly to the circuit 6 via the multiplexer 8. Thus it is possible to perform the binary calculation of 1/2*(3-AXi) where 0