Abstract: We examine the problem of routing wires on a VLSI chip, where the pins to be connected are arranged in a regular rectangular array. We obtain tight bounds for the worst-case "channel-width" needed to route an n × n array, and develop provably good heuristics for the general case. An interesting "rounding algorithm" for obtaining integral approximations to solutions of linear equations is used to show the near-optimality of single-turn routings in the worst-case.

Abstract: The foundations of an arithmetic unit performing the add, subtract, multiply, and divide operations on rational operands are developed. The unit uses the classical Euclidean algorithm as one unified algorithm for all the arithmetic operations, including rounding. Binary implementations are discussed, based on techniques known from SRT division, and utilizing ripple-free borrow-save and carry-save addition. Average time behavior is investigated.

Abstract: A higher-radix division algorithm with simple selection of quotient digits is described. The proposed scheme is a combination of the multiplicative normalization used in the continued-product algorithms and the recursive division algorithm. The scheme consists of two parts: in the first part, the divisor and the dividend are transformed into the range which allows the quotient digits to be selected by rounding partial remainders to the most significant radix-r digit in the second part. Since the selection requires only the most significant part of the partial remainder, limited carry-propagation adders can be used to form the partial remainders. The divisor and dividend transformations are performed in three steps using multipliers of the form 1 + s k r−k as in the continued product algorithm. The higher radix of the form r = 2k, k=2,4,8,…, can be used to reduce the number of steps while retaining the simple quotient selection rules.

Abstract: Single-precision floatingpoint computations may yield an arbitrary false result due to cancellation and rounding errors. This is true even for very simple, structured arithmetic expressions such as Horner's scheme for polynomial evaluation. A simple procedure will be presented for fast calculation of the value of an arithmetic expression to least significant bit accuracy in single precision computation. For this purpose in addition to the floating-point arithmetic only a precise scalar product (cf. [2]) is required. If the initial floatingpoint approximation is not too bad, the computing time of the new algorithm is approximately the same as for usual floating-point computation. If not, the essential progress of the presented algorithm is that the inaccurate approximation is recognized and corrected. The algorithm achieves high accuracy, i.e. between the left and the right bound of the result there is at most one more floating-point number. A rigorous estimation of all rounding errors introduced by floating-point arithmetic is given for general triangular linear systems. The theorem is applied to the evaluation of arithmetic expressions.

Abstract: The steady state output error of the Least Mean Square (LMS) Adaptive Algorithm due to the finite precision arithmetic of a digital processor is analyzed. It is found to consist of three terms: (1) the error due to the input data quantization, (2) the error due to the rounding of the arithmetic operations in calculating the filter's output, and (3) the error due to the deviation of the filter's coefficients from the values they take when infinite precision arithmetic is used. The last term is inversely proportional to the adaptation step size µ. Both fixed and floating point arithmetics are examined. The relation between the quantization error and the error that occurs when adaptation possibly ceases due to quantization is also investigated.

Abstract: This paper examines the utility of linear predictive coding in reducing the amount of data storage required for signals gathered in ocean bottom seismology. In this study, a set of 12 typical signals were repeatedly encoded with the storage allocated decreasing from an initial 12 bits per datum to 2. The error introduced was then compared to the performance achieved by simply rounding off the lowest bits of the data, and to estimates of the rate distortion limit. It was found that this scheme consistently introduced about 15 times (4 bits) less distortion both in terms of the root-mean-square (rms) error and in terms of the maximum error than rounding the data. Moreover, the rms distortion of the data were within a factor of 4 (2 bits) of the rate distortion bound on optimal encoding. Thus, the scheme was seen to be an effective approach to the problem of data compression in the marine environment.

Abstract: In this paper we establish a forward error analysis of the generalized complete Horner scheme for a polynomial $$p = \sum {a_j X^{n - j} } $$ with pivotal pointsz 1, ...,z n . The error analysis is based on the linearization method whose fundamental tools are systems of linear error equations and associated condition numbers which yield optimal bounds of the possible errors under data perturbations and rounding errors in floating point arithmetic. For Horner's scheme the bounds may be calculated by simple recurrences. The ordinary complete Horner scheme is characterized byz=z 1=...=z n . In contrast to the hitherto known error estimates for this special case our new optimal bounds for the polynomialp atz differ from those for the polynomial $$p_a = \sum {\left| {a_j } \right|X^{n - j} } $$ at |z| and thus take into account the possible partial cancellation of terms. The error estimates are illustrated by a series of numerical examples.

Abstract: PURPOSE:To show the deformation of characters with a small number of parameters and to attain the quantization for the degree of character deformation, by taking a simple constitution in which the irregular perturbation to the standard character form to generate a deformed character. CONSTITUTION:A signal for initialization is fed to a smoothing circuit 220, a deformation degree arithmetic circuit 250, a rounding circuit 270 and a deformed pattern memory 280 respectively from a control part 290. Then a random number generating circuit 210 produces a single unit of the uniform random number with a timing signal sent through a connection 2901 and sends it to the circuit 220. Further, the timing signal is sent to a perturbation arithmetic circuit 240 through a radio 2902, and the circuit 240 reads the coordinate value of a standard character form and the angle of the normal direction out of a standard character form storing memory 230. The circuit 270 performs a rounding process on the basis of the coordinate value given from the circuit 240 and writes the result of the rounding process to the memory 280. The circuit 250 gives the replacement to the degree of deformation of characters.

Abstract: A fast leading/trailing-zero detection circuit (LZDC/TZDC) is described, and then applied to the design of a pipelined floating-point (FLP) processor. This circuit has a total delay of 5Δ and a hardware complexity of (m + 1)(3 \log_{2}(p) + 4) where Δ, m , and p are the unit gate delay, subword number, and subword partition length, respectively. Applications of this circuit to both postnormalization and rounding are presented, including circuits for normalization, sticky bit generation, and increment-by-one. The LZDC/TZDC has two important features-modularity and expandability-which make it particularly well suited for VLSI implementation.

Abstract: A family of monotonic difference schemes on a non-uniform mesh is proposed for solving a second-order ordinary differential equation with a small parameter in the highest derivative. It is shown that, under certain conditions on the coefficients of the equation, the difference scheme is ill-posed. Two methods are given for solving an ill-posed difference problem, which are stable to rounding errors.

Abstract: Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.

Abstract: PURPOSE:To obtain a processor which rounds off binary data speedily only by binary arithmetic without performing binary and decimal mutual conversion, by providing a register which holds a numeral to be rounded. CONSTITUTION:The 1st register holds a numeral to be rounded, and the 2nd register holds the number of digits of which numerals are to be rounded off. For example, the 1st register REG1 holds binary data Z to be rounded, the 2nd register REG2 holds the number N of digits to be disregarded by the rounding of a decimal number that the binary data represents, and the 3rd register REG3 holds a numeral (n) obtained by subtracting a constant 1 from the number N of digits. Then, a division control part DIV1 divides the numeral Z in the REG1 by a numeral obtained by multiplying the value (n) in the REG3 by a factor 10, and an adding circuit ADD adds a constant 5 to the quotient obtained by the DIV1. Then, a division control part DIV2 divides the output of the ADD by a constant 10 and its quotient Z is held in the 4th register REG4.

Abstract: Earlier authors have shown experimentally that the relative effect of rounding errors in the evaluation of polynomial approximations to certain special functions may be significantly reduced by first extracting an exponential factor. The critical importance of evaluating this exponential by an accurate library function is demonstrated, and the two principal methods of representing the polynomial part are shown to be equally accurate provided the recommended evaluation schemes are employed.

Abstract: A modified form of Papoulis's trigonometric algorithm for Laplace inversion is described; it amounts to summation of a finite number of values of the transform with previously computed coefficients, and avoids computer evaluation of elementary functions, thus minimizing the number of operations when finding. the original approximately. The rounding errors are analyzed.

Abstract: Fraction number systems described by fixed-slash and floating slash formats are specified. The structure of arithmetic over such systems is prescribed by the rounding obtained from ''best rational approximation''. Multi-tiered precision hierarchies of both fixed-slash and floating-slash type are proposed and analyzed with regards to their support of both exact rational and approximative real computation.

Abstract: An attempt is made to analyze the fixed point error performance of the normalized ladder algorithm, for autoregressive system identification, assuming rounding arithmetic. A preliminary simulation study of this algorithm has shown that the bias in the estimated reflection coefficients is much more predominant than the variance of the error in the estimate. The study, therefore, is directed to find a model for predicting the bias in the estimated reflection coefficients. The analysis shows that the roundoff errors associated with the square root operations in one of the algorithm equations are mainly responsible for the bias in the estimated reflection coefficients. These errors arise because of the normalization procedure that makes the quantities under the square root operations very close to one. Two main results are presented in the paper. 1) A simplified theoretical expression for predicting the average bias in the estimated reflection coefficients at any stage is derived. 2) A recursive relation for the average error, arising from the finite precision arithmetic in the squared residuals, is derived. This relation illustrates how the errors made in one stage affect the errors in the succeeding stages. Simulations are performed to check the theoretical models. The experimental results agree very closely with the theoretical predictions.

Abstract: FIR digital filters with discrete coefficient values selected from the powers-of-two coefficient space are designed using the methods of integer programming. The frequency responses obtained are shown to be superior to those obtained by simply rounding the coefficients. Both the weighted minimax and the weighted least square error criteria are considered. Using a weighted least square error criterion, it is shown that it is possible to predict the improvement that can be expected when integer quadratic programming is used instead of simple coefficient rounding.