Reset vector

Abstract: A method for increasing boot speed of a host computer with associated hard disk drive generates a prefetch table that contains pointers to disk locations and lengths of the records of an application program requested by the host computer during an initial power-on/reset. During the next power-on/reset, before the host computer is ready for data but after the disk drive has completed its reset routine, using the prefetch table the disk drive accesses the previously requested data and copies it onto the cache of the disk drive, from where it is transferred to the host computer when the host computer requests it. The prefetch table is updated to reflect disk location changes for the various records, or to reflect new records that were requested by the host computer but not found in cache during the previous power-on/reset.

Abstract: A shutter system for a pixel array is disclosed. The system includes a read shift register, first and second reset shift registers, and a plurality of logic gates. The read shift register is configured to sequentially count rows of the pixel array from top to bottom, such that the read shift register generates a read pointer. The first reset shift register is configured to sequentially reset rows of the pixel array from top to bottom. The first reset shift register provides a first reset pointer for allowing reset of pixels in a row indicated by the first reset pointer. The first reset pointer allows reset of pixels prior to reading of the pixels in a row indicated by the read pointer. The time difference between the first reset pointer and the read pointer indicates an exposure time. The second reset shift register is configured to provide a second reset pointer, which enables the first reset shift register to sequentially reset rows of the pixel array without generating any flashes when the exposure time is increased. The plurality of logic gates direct outputs of the read shift register and the first and second reset shift registers to each pixels in the pixel array.

Abstract: A semiconductor microcontroller device is adapted to control the operation of an external system. The device includes a CPU, program memory for storing instructions to be executed by the CPU to perform its control functions, and data memory for storing data for selective retrieval by the CPU. The contents of either memory are code protected by an EEPROM fuse, and are automatically erased if the code protect state of the EEPROM fuse is sought to be reset, and the EEPROM fuse is reset only after the erasure of the memory contents.

Abstract: A video signal encoding system includes a signal processor for segmenting encoded video data into transport blocks having a header section and a packed data section. The system also includes reset control apparatus for releasing resets of system components, after a global system reset, in a prescribed non-simultaneous phased sequence to enable signal processing to commence in the prescribed sequence. The phased reset release sequence begins when valid data is sensed as transiting the data lines.