Render output unit

Abstract: A system for rendering visual images that combines sophisticated anti-aliasing and pixel blending techniques with control pipelining in hardware embodiment. A highly-parallel rendering pipeline performs sophisticated polygon edge interpolation, pixel blending and anti-aliasing rendering operations in hardware. Primitive polygons are transformed to subpixel coordinates and then sliced and diced to create "pixlink" elements mapped to each pixel. An oversized frame buffer memory allows the storage of many pixlinks for each pixel. Z-sorting is avoided through the use of a linked-list data object for each pixlink vector in a pixel stack. Because all image data values for X, Y, Z, R, G, B and pixel coverage A are maintained in the pixlink data object, sophisticated blending operations are possible for anti-aliasing and transparency. Data parallelism in the rendering pipeline overcomes the processor efficiency problem arising from the computation-intensive rendering algorithms used in the system of this invention. Single state machine control is made possible through linked data/control pipelining.

Abstract: PROBLEM TO BE SOLVED: To accomplish an efficient full scene anti-aliasing. SOLUTION: This graphics system can separately select three sampling positions in each super sampling pixel about a 2×2 pixel group (quadruplet). A 12-bit multi-sample application range mask decides which is enabled among twelve samples in the pixel quadruplet. The super sampling pixel is filtered during copyout operation from a local memory to an external buffer memory by using a pixel blend filter for connecting seven samples (three samples from present pixels and two samples from pixels just over and under the present pixels, respectively) from the three vertically displaced pixels. A weighted average is calculated on the basis of the enabled sample in order to decide the last color of the pixels.

Abstract: The paper proposes additional evaluation functions to mark the segment area that cuts straight line to determine the intensity of the color pixel. For anti-aliasing purposes a twelve-angle pixel model is suggested. Additional evaluation functions are used to identify the pixel color intensity. These functions can be calculated independently. A structure of a device is proposed for hardware implementation of anti-aliasing.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.