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  3. Reliability (semiconductor)
  4. 2018
Showing papers on "Reliability (semiconductor) published in 2018"
Journal Article•10.1109/TPEL.2017.2665697•
Junction Temperature Control for More Reliable Power Electronics

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Markus Andresen1, Ke Ma2, Giampaolo Buticchi1, Johannes Falck1, Frede Blaabjerg3, Marco Liserre1 •
University of Kiel1, Shanghai Jiao Tong University2, Aalborg University3
01 Jan 2018-IEEE Transactions on Power Electronics
TL;DR: In this article, possible approaches to control the semiconductor junction temperature are discussed along with the implementation in several emerging applications, and the modification of the control variables at different levels (modulation, control, and system) to alter the loss generation or distribution is analyzed.
Abstract: The thermal stress of power electronic components is one of the most important causes of their failure. Proper thermal management plays an important role for more reliable and cost-effective energy conversion. As one of the most vulnerable and expensive components, power semiconductor components are the focus of this paper. Possible approaches to control the semiconductor junction temperature are discussed in this paper, along with the implementation in several emerging applications. The modification of the control variables at different levels (modulation, control, and system) to alter the loss generation or distribution is analyzed. Some of the control solutions presented in the literature, which showed experimentally that the thermal stress can be effectively reduced, are reviewed in detail. These results are often mission-profile dependent and the controller needs to be tuned to reach the desired cost-benefit tradeoff. This paper analyzes also the many open questions of this research area. Among them, it is worth highlighting that a verification of the actual lifetime extension is still missing.

310 citations

Proceedings Article•
Design for Reliability in Power Electronic Systems

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Frede Blaabjerg1•
Aalborg University1
1 Sep 2018
TL;DR: A collection of methodologies based on Physics-of-Failure approach and mission profile analysis are presented in this paper to perform reliability-oriented design of power electronic systems and corresponding design procedures and reliability prediction models are provided.
Abstract: In recent years, the automotive and aerospace industries have brought stringent reliability constraints on power electronic converters because of safety requirements. Today customers of many power electronic products expect up to 20 years (or even longer) of lifetime and they also want to have a "failure free period" and all with focus on the financials. The renewable energy sectors are also following the same tred, and more and more efforts are being devoted to improving power electronic converters to account for reliability with cost-effective and sustainable solutions. This presentation will introduce the recent progress in the reliability aspect study of power electronic converters for power electronic applications with special focus on renewables. It will cover the following contents: the motivations for highly reliable electric energy conversion in renewables; the reliability requirements of typical power electronic systems; failure mechanisms and lifetime models of key power electronic components (e.g., power semiconductor switches, capacitors, and fans); long-term mission profiles in renewable applications and their components; reliability analysis methods for more complicated systems, tools to be applied, and improvement strategies of power electronic converters in their applications. A few case studies will be given.

261 citations

Journal Article•10.3390/APP8040534•
Battery Management System Hardware Concepts: An Overview

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Markus Lelie, Thomas Braun, Marcus Knips, Hannes Nordmann, Florian Ringbeck, Hendrik Zappen, Dirk Uwe Sauer 
30 Mar 2018-Applied Sciences
TL;DR: This paper focuses on the hardware aspects of battery management systems (BMS) for electric vehicle and stationary applications, giving an overview on existing concepts in state-of-the-art systems and enabling the reader to estimate what has to be considered when designing a BMS for a given application.
Abstract: This paper focuses on the hardware aspects of battery management systems (BMS) for electric vehicle and stationary applications. The purpose is giving an overview on existing concepts in state-of-the-art systems and enabling the reader to estimate what has to be considered when designing a BMS for a given application. After a short analysis of general requirements, several possible topologies for battery packs and their consequences for the BMS’ complexity are examined. Four battery packs that were taken from commercially available electric vehicles are shown as examples. Later, implementation aspects regarding measurement of needed physical variables (voltage, current, temperature, etc.) are discussed, as well as balancing issues and strategies. Finally, safety considerations and reliability aspects are investigated.

238 citations

Journal Article•10.1109/TPEL.2017.2690500•
Power Cycling Test Methods for Reliability Assessment of Power Device Modules in Respect to Temperature Stress

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Ui-Min Choi1, Frede Blaabjerg1, Soren Jorgensen•
Aalborg University1
01 Mar 2018-IEEE Transactions on Power Electronics
TL;DR: In this paper, representative power cycling test circuits, measurement circuits of wear-out failure indicators as well as measurement strategies for different power cycle test circuits are discussed in order to provide the current state of knowledge of this topic by organizing and evaluating current literature.
Abstract: Power cycling test is one of the important tasks to investigate the reliability performance of power device modules in respect to temperature stress. From this, it is able to predict the lifetime of a component in power converters. In this paper, representative power cycling test circuits, measurement circuits of wear-out failure indicators as well as measurement strategies for different power cycling test circuits are discussed in order to provide the current state of knowledge of this topic by organizing and evaluating current literature. In the first section of this paper, the structure of a conventional power device module and its related wear-out failure mechanisms with degradation indicators are discussed. Then, representative power cycling test circuits are introduced. Furthermore, on-state collector–emitter voltage $(V_{{\rm{CE\_ON}}})$ and forward voltage $(V_{F})$ measurement circuits for wear-out condition monitoring of power device modules during power cycling test are presented. Finally, different junction temperature measurement strategies for monitoring of solder joint degradation are explained.

227 citations

Journal Article•10.1002/AENM.201702116•
Effect of Cation Composition on the Mechanical Stability of Perovskite Solar Cells

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Nicholas Rolston1, Adam D. Printz1, Jared Tracy1, Hasitha Weerasinghe2, Doojin Vak2, Lew Jia Haur3, Anish Priyadarshi3, Nripan Mathews3, Daniel J. Slotcavage1, Michael D. McGehee1, Roghi E. Kalan4, Kenneth Zielinski4, Ronald L. Grimm4, Hsinhan Tsai5, Wanyi Nie5, Aditya D. Mohite5, Somayeh Gholipour6, Michael Saliba6, Michael Grätzel6, Reinhold H. Dauskardt1 •
Stanford University1, Commonwealth Scientific and Industrial Research Organisation2, Nanyang Technological University3, Worcester Polytechnic Institute4, Los Alamos National Laboratory5, École Polytechnique Fédérale de Lausanne6
01 Mar 2018-Advanced Energy Materials
Abstract: Photoactive perovskite semiconductors are highly tunable, with numerous inorganic and organic cations readily incorporated to modify optoelectronic properties. However, despite the importance of device reliability and long service lifetimes, the effects of various cations on the mechanical properties of perovskites are largely overlooked. In this study, the cohesion energy of perovskites containing various cation combinations of methylammonium, formamidinium, cesium, butylammonium, and 5‐aminovaleric acid is reported. A trade‐off is observed between the mechanical integrity and the efficiency of perovskite devices. High efficiency devices exhibit decreased cohesion, which is attributed to reduced grain sizes with the inclusion of additional cations and PbI2 additives. Microindentation hardness testing is performed to estimate the fracture toughness of single‐crystal perovskite, and the results indicated perovskites are inherently fragile, even in the absence of grain boundaries and defects. The devices found to have the highest fracture energies are perovskites infiltrated into a porous TiO2/ZrO2/C triple layer, which provide extrinsic reinforcement and shielding for enhanced mechanical and chemical stability.

161 citations

Journal Article•10.3390/ELECTRONICS7120377•
A Comprehensive Review of Recent Progress on GaN High Electron Mobility Transistors: Devices, Fabrication and Reliability

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Fanming Zeng, Judy Xilin An, Guangnan Zhou, Wenmao Li, Hui Wang, Tianli Duan, Jiang Lingli, Hongyu Yu 
03 Dec 2018-Electronics
TL;DR: In this paper, the authors review recent progress in AlGaN/GaN HEMTs, including the following sections: challenges in device fabrication and optimizations, and some promising device structures from simulation studies.
Abstract: GaN based high electron mobility transistors (HEMTs) have demonstrated extraordinary features in the applications of high power and high frequency devices. In this paper, we review recent progress in AlGaN/GaN HEMTs, including the following sections. First, challenges in device fabrication and optimizations will be discussed. Then, the latest progress in device fabrication technologies will be presented. Finally, some promising device structures from simulation studies will be discussed.

148 citations

Proceedings Article•10.1109/IEDM.2018.8614710•
Vertical Ferroelectric HfO 2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory

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Karine Florent1, Milan Pešić, A. Subirats1, K. Banerjee1, Simone Lavizzari, Antonio Arreghini1, L. Di Piazza1, Goedele Potoms1, Farid Sebaai1, S. R. C. McMitchell1, Mihaela Popovici1, Guido Groeseneken1, J. Van Houdt1 •
Katholieke Universiteit Leuven1
1 Dec 2018
TL;DR: In this article, a vertical ferroelectric HfO 2 field effect transistor based on 3-D macaroni NAND architecture is reported for the first time, with a flash-like endurance of 104 cycles.
Abstract: A vertical ferroelectric HfO 2 field effect transistor based on 3-D macaroni NAND architecture is reported for the first time. Up to 2 V memory window was obtained after the application of 100 ns program/erase pulses. Flash-like endurance of 104 cycles is reported and first reliability assessments were performed.

143 citations

Journal Article•10.1016/J.RSER.2017.10.096•
Hierarchical structure and bus voltage control of DC microgrid

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Zhikang Shuai1, Fang Junbin1, Fenggen Ning1, Z. John Shen2•
Hunan University1, Illinois Institute of Technology2
01 Feb 2018-Renewable & Sustainable Energy Reviews
TL;DR: In this paper, an extensive review on the hierarchical structure of the DC microgrid is applied, and two typical control structures are presented in detail: two-level control architecture and three level control architecture.
Abstract: Compared to AC microgrids, DC microgrids have the advantage of higher reliability and efficiency and are convenient to connect with various distribution energy resources (DERs). Concentrated in different time-scale control objectives, a multi-level control structure can guarantee that none of the control objectives affect each other. Considering this, an extensive review on the hierarchical structure of the DC microgrid is applied, and two typical control structures are presented in detail: two-level control architecture and three-level control architecture. Furthermore, the primary, secondary, and tertiary control levels are systematically analyzed and classified according to different control objectives. In order to improve the control capability of the primary control level, an energy efficiency improved DC bus voltage control strategy is proposed to increase the energy efficiency and system reliability. Finally, a distributed DC microgrid model is established and simulated in the RT-LAB to verify the effectiveness of the proposed control strategy.

135 citations

Journal Article•10.1109/TPEL.2017.2691668•
Bus Bar Design for High-Power Inverters

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Alan Dorneles Callegaro1, Jing Guo1, Michael Eull2, Benjamin Danen1, Jason Gibson, Matthias Preindl2, Berker Bilgin1, Ali Emadi1 •
McMaster University1, Columbia University2
01 Mar 2018-IEEE Transactions on Power Electronics
TL;DR: This paper presents a comprehensive analysis about bus bar design procedure and the effects of stray inductance and capacitance are explained along with the dc-link capacitors and power semiconductor devices.
Abstract: This paper presents a comprehensive analysis about bus bar design procedure. Some applications in terms of rated power and shape are investigated regarding their particular requirements and challenges. The dc-link capacitor selection is one of the first and most important steps. It not only dictates the bus bar complexity but also is the key to accomplish a high-power density prototype. Current density and distribution is discussed in this paper based on simulation results. Moreover, the effects of stray inductance and capacitance are explained along with the dc-link capacitors and power semiconductor devices. Simulated results are compared with measurements by a high precision impedance analyzer, which shows the reliability of 3-D modeling-based designs.

109 citations

Journal Article•10.1109/MPEL.2018.2874345•
Failure Analysis of the dc-dc Converter: A Comprehensive Survey of Faults and Solutions for Improving Reliability

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Levy Costa, Marco Liserre1•
University of Kiel1
19 Dec 2018-IEEE Power Electronics Magazine
TL;DR: The failure in dc-dc converters is investigated, with the aim to identify the most vulnerable devices and discuss solutions for improving the converter's availability.
Abstract: In many industrial applications, power interruption is not tolerated, and a highly reliable power electronics system is required. In fact, a failure on the power converter penalizes not only the maintenance cost (to repair or change the converter), but also the operational cost, because the service is interrupted. Thus, this article investigates the failure in dc-dc converters, with the aim to identify the most vulnerable devices and discuss solutions for improving the converter's availability.

109 citations

Journal Article•10.1038/S41928-018-0148-3•
Integrated microthermoelectric coolers with rapid response time and high device reliability

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Guodong Li1, Javier Garcia Fernandez1, David Alberto Lara Ramos2, David Alberto Lara Ramos1, David Alberto Lara Ramos3, Vida Barati1, Vida Barati2, Nicolás Pérez1, Ivan Soldatov1, Heiko Reith1, Gabi Schierning1, Kornelius Nielsch1, Kornelius Nielsch2 •
Leibniz Association1, Dresden University of Technology2, Consejo Nacional de Ciencia y Tecnología3
1 Oct 2018
TL;DR: In this article, the authors report the fabrication of µ-TECs that offer a rapid response time of 1 ms, reliability of up to 10 million cycles and cooling stability of more than 1 month at constant electric current.
Abstract: Microthermoelectric modules are of potential use in fields such as energy harvesting, thermal management, thermal imaging and high-spatial-resolution temperature sensing. In particular, microthermoelectric coolers (µ-TECs)—in which the application of an electric current cools the device—can be used to manage heat locally in microelectronic circuits. However, a cost-effective µ-TEC device that is compatible with the modern semiconductor fabrication industry has not yet been developed. Furthermore, the device performance of µ-TECs in terms of transient responses, cycling reliability and cooling stability has not been adequately assessed. Here we report the fabrication of µ-TECs that offer a rapid response time of 1 ms, reliability of up to 10 million cycles and a cooling stability of more than 1 month at constant electric current. The high cooling reliability and stability of our µ-TEC module can be attributed to a design of free-standing top contacts between the thermoelectric legs and metallic bridges, which reduces the thermomechanical stress in the devices. A free-standing top contact design reduces the thermomechanical stress in microthermoelectric coolers, resulting in improved reliability and cooling stability.
Proceedings Article•10.1109/IRPS.2018.8353648•
Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG

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Anisur Rahman1, Javier Dacuna1, P. Nayak1, Gerald S. Leatherman1, S. Ramey1 •
Intel1
11 Mar 2018
TL;DR: It is reported that Intel's 10nm technology achieved scaling benefit over its preceding 14nm generation at matched or better transistor reliability.
Abstract: Development of an industry leading 10nm CMOS process technology with the highest reported drive currents and cell densities involved numerous enabling innovations, judicious choice of design rules, novel features, and most importantly a relentless pursuit of performance-reliability co-optimization. This paper reports that Intel's 10nm technology achieved scaling benefit over its preceding 14nm generation at matched or better transistor reliability. An elaborate study of the challenges to scaling is presented, which once addressed, enabled meeting aggressive technology reliability targets.
Journal Article•10.1109/MIE.2018.2874385•
Physical-Layer Security for Industrial Wireless Control Systems: Basics and Future Directions

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Fei Pan, Zhibo Pang, Michele Luvisotto, Ming Xiao1, Hong Wen2 •
Royal Institute of Technology1, University of Electronic Science and Technology of China2
19 Dec 2018-IEEE Industrial Electronics Magazine
TL;DR: The principles of PHY-Sec, its application to wireless control systems, and potential research directions are discussed, including possible research directions for physical (PHY)-layer security technology.
Abstract: Wireless networks for industrial control systems are promising because of their reduced cost, flexible structure, and improved long-term reliability. However, wireless control systems are vulnerable to probing-free attacks (PFAs), which are not possible in wired control systems. Thus, wireless control systems must be made as secure as wired systems. Physical (PHY)-layer security technology (PHY-Sec) may be a new strategy for securing industrial wireless control systems. Among all PHY-Sec technologies, PHY-layer authentication is the first step for PHYSec in industrial wireless control systems. This article discusses the principles of PHY-Sec, its application to wireless control systems, and potential research directions.
Journal Article•10.1049/IET-RPG.2017.0219•
Impact of grid-tied large-scale photovoltaic system on dynamic voltage stability of electric power grids

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Shady S. Refaat1, Haitham Abu-Rub1, Antonio Sanfilippo2, Amira Mohamed1•
Texas A&M University1, Qatar Airways2
01 Feb 2018-Iet Renewable Power Generation
TL;DR: This study investigates and reports on the dynamic stability of the power system with a large-scale photovoltaic system (L-S PV) and two different scenarios with centralised PV power plants are considered in the medium voltage level without voltage regulation capabilities.
Abstract: Perfect power system voltage stability is not possible in practice Generally, the power grid is continually exposed to changes in its load and operating conditions Therefore, dynamic stability analysis is one the most important and effective elements for greater security, stability and reliability of planning, design, operation and economic aspects of electric power networks This study investigates and reports on the dynamic stability of the power system with a large-scale photovoltaic system (L-S PV) Two different scenarios with centralised PV power plants are considered in the medium voltage level without voltage regulation capabilities Simulation results with these scenarios will show how the voltage instability decreases with the L-S PV based on the bus status, disturbance location, and disturbance duration In addition, the study discusses network terminal voltage, generator's rotor angle, generator's terminal current, generator's reactive power and electrical power output This study is an extension of the earlier published conference paper
Journal Article•10.1016/J.JALLCOM.2018.04.040•
Materials, processing and reliability of low temperature bonding in 3D chip stacking

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Liang Zhang1, Liang Zhang2, Zhi-Quan Liu2, Sinn-wen Chen3, Yaodong Wang4, Long Weimin, Guo Yonghuan1, Song-quan Wang1, Guo Ye1, Wen-yi Liu1 •
Jiangsu Normal University1, Chinese Academy of Sciences2, National Tsing Hua University3, Intel4
25 Jun 2018-Journal of Alloys and Compounds
TL;DR: In this paper, different low temperature bonding methods for chip (or wafer) stacking were reviewed and described systematically, and their effects on the 3D IC structure were addressed in detail, the challenging reliability issues may be considered as the major concern in the future work.
Book•
Electric Power Grid Reliability Evaluation: Models and Methods

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Chanan Singh, Panida Jirutitijaroen, Joydeep Mitra
11 Dec 2018
TL;DR: This book is a guide to the theoretical approaches and processes that underpin the electric power grid and reviews the most current and emerging technologies designed to ensure reliability.
Abstract: Electric Power Grid Reliability Evaluation deals with the effective evaluation of the electric power grid and explores the role that this process plays in the planning and designing of the expansion of the power grid. The book is a guide to the theoretical approaches and processes that underpin the electric power grid and reviews the most current and emerging technologies designed to ensure reliability. The authors—noted experts in the field—also present the algorithms that have been developed for analyzing the soundness of the power grid.
Journal Article•10.23919/CJEE.2018.8471284•
A comprehensive survey on fault diagnosis and fault tolerance of DC-DC converters

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Fernando Bento1, Antonio J. Marques Cardoso1•
University of Beira Interior1
27 Sep 2018
TL;DR: An up-to-date review of the recent achievements attained regarding the improvement of availability and reliability of DC-DC converters is presented.
Abstract: DC-DC converters are becoming more commonly used in power conversion solutions for energy management purposes, being employed in an ever-increasing range of DC-based applications, such as LED lighting, electric vehicles, energy storage solutions, and consumer electronics (laptops, smartphones, etc.). In this context, efficiency and reliability are critical. The research efforts made in improving reliability of DC-DC converters are still quite narrow and scattered. Moreover, DC-DC converters take the shape of an endless number of topologies, with different functionalities and operation principles, thus complicating the task of improving reliability of all forms of DC-DC converters. Consequently, compiling the information about the main failure modes, corresponding fault diagnostic algorithms and fault tolerance strategies developed so far, in a single document, becomes increasingly necessary. Accordingly, this paper presents an up-to-date review of the recent achievements attained regarding the improvement of availability and reliability of DC-DC converters.
Journal Article•10.1109/LED.2018.2821923•
Sub-100 nm 2 Cobalt Interconnects

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Shibesh Dutta1, Sofie Beyne1, Anshul Gupta1, Shreya Kundu1, Sven Van Elshocht1, Hugo Bender1, G. Jamieson1, Wilfried Vandervorst1, Jürgen Bömmels1, Christopher J. Wilson1, Zsolt Tokei1, Christoph Adelmann1 •
Katholieke Universiteit Leuven1
02 Apr 2018-IEEE Electron Device Letters
TL;DR: In this paper, the authors demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique, and the resistivity and the reliability of the Co wires are comparable with those of Ru wires.
Abstract: Co has elicited a strong interest to replace Cu for future interconnect applications in microelectronic circuits due to its potentially lower resistivity and better reliability at scaled dimensions. Here, we demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique. Semiclassical resistivity modeling of the wire resistivity indicates that grain boundary scattering is the dominant contribution for cross-sectional areas of the order of 100 nm2, while the contribution of surface scattering increases drastically below 50 nm2. Furthermore, wafer-level reliability tests of the Co wires show the high fusing current densities and a strong resistance to thermoelectric stress demonstrating the potential for robust reliability. The resistivity and the reliability of the Co wires are comparable with those of Ru wires.
Journal Article•10.1109/ACCESS.2018.2811904•
Fault-Tolerant Control of Medium-Voltage Modular Multilevel Converters With Minimum Performance Degradation Under Submodule Failures

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Binbin Li1, Zigao Xu1, Jian Ding1, Dianguo Xu1•
Harbin Institute of Technology1
08 Mar 2018-IEEE Access
TL;DR: A novel fault-tolerant modulation and control strategy is proposed for MMC in medium voltage applications and provides optimum performances under healthy conditions and minimum performance degradation after SM failures.
Abstract: As the state-of-the-art voltage-source topology, the modular multilevel converter (MMC) is attractive for various medium- or high-power applications. In MMC, reliability and uninterruptable operation are always seen as primary concerns, which requires the MMC can continue operating even though some of the submodules (SMs) are failed. In this paper, a novel fault-tolerant modulation and control strategy is proposed for MMC in medium voltage applications. Compared with previous works, the proposed strategy provides optimum performances under healthy conditions and minimum performance degradation after SM failures. During healthy conditions, the redundant SMs are fully utilized to decrease SM capacitor voltage for higher reliability and to reduce switching frequency for higher efficiency. While during fault-tolerant operation, by appropriate modification of the modulation and controllers, no extra healthy SMs need to be bypassed and the output voltage harmonics of MMC remain unchanged without causing voltage mismatches. Feasibility and effectiveness of the proposed strategy have been verified by simulations in MATLAB/Simulink software and experiments on a downscaled three-phase MMC prototype.
Proceedings Article•10.1109/IRPS.2018.8353641•
Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology

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Flavio Griggio1, J. Palmer1, F. Pan1, N. Toledo1, A. Schmitz1, I. Tsameret1, Rahim Kasim1, Gerald S. Leatherman1, J. Hicks1, A. Madhavan1, J. Shin1, Joseph M. Steigerwald1, Yeoh Andrew W1, C. Auth1 •
Intel1
11 Mar 2018
TL;DR: Intrinsic TDDB reliability for Co/ low-k ILD meets the expectations and surpasses the capability of Cu/low- k ILD systems with E-field acceleration factor of ∼5 cm/MV using E-model fit.
Abstract: This paper discusses the reliability of a new metallization scheme for 10nm back end of line (BEOL) local interconnect. Electromigration (EM) and time dependent dielectric breakdown (TDDB) on cobalt fill interconnects are investigated. Significant innovation in process manufacturing are delivered to meet the reliability challenges of technology scaling. Electromigration time to failure is observed to be at least four orders of magnitude higher for Co fill interconnects compared to Cu alloy metallurgy. Intrinsic TDDB reliability for Co/low-k ILD meets the expectations and surpasses the capability of Cu/low-k ILD systems with E-field acceleration factor of ∼5 cm/MV using E-model fit. Wafer level stress induced voiding reliability on Co shows superior intrinsic properties with respect to Cu.
Journal Article•10.1109/TPEL.2017.2717183•
A Grid-Voltage-Sensorless Resistive-Active Power Filter With Series LC-Filter

[...]

Haofeng Bai1, Xiongfei Wang1, Frede Blaabjerg1•
Aalborg University1
01 May 2018-IEEE Transactions on Power Electronics
TL;DR: A grid-voltage-sensorless control strategy is proposed for the R-APF with series LC-filter and shows good accuracy of the emulated resistance and functionality of the DC-link voltage control.
Abstract: Voltage-sensorless control has been investigated for voltage source inverters (VSIs) for many years due to the reduced system cost and potentially improved system reliability. The VSI-based resistive-active power filters (R-APFs) are now widely used to prevent the harmonic resonance in power distribution network, for which the voltage sensors are needed in order to obtain the current reference. In this paper, a grid-voltage-sensorless control strategy is proposed for the R-APF with series LC -filter. Unlike the traditional resistance emulation method, this proposed control method reshapes the output impedance of the R-APF at the harmonic frequencies, which is independent of the current reference. A fundamental grid-voltage estimation method is also proposed to control the dc-link voltage. The performance of the proposed control method is verified in both simulations and experiments. The results show good accuracy of the emulated resistance and functionality of the dc-link voltage control. With the proposed method, the cost of the R-APF can also be reduced with potentially improved system reliability.
Journal Article•10.1080/17517575.2018.1450998•
Big data driven cycle time parallel prediction for production planning in wafer manufacturing

[...]

Junliang Wang1, Jungang Yang2, Jie Zhang1, Xiaoxi Wang1, Wenjun Chris Zhang1 •
Donghua University1, Shanghai Jiao Tong University2
21 Mar 2018-Enterprise Information Systems
TL;DR: A novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets and can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods.
Abstract: Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a nov...
Proceedings Article•10.1109/ISPSD.2018.8393704•
Power cycling reliability results of GaN HEMT devices

[...]

Jörg Franke1, Guang Zeng1, Tom Winkler1, Josef Lutz1•
Chemnitz University of Technology1
13 May 2018
TL;DR: In this paper, the main failure mechanism of the GaN HEMT from two different manufacturers under power cycling tests is the degradation of solder layer between device and printed circuit board.
Abstract: The GaN HEMT is a novel wide bandgap device which could improve the overall efficiency and at the same time shrink the system size. In order to verify the reliability of this promising semiconductor device, new measurement and testing methods have to be developed. In this work, as a general basis for performing reliability tests junction temperature measurement methods for GaN HEMT were investigated. By using suitable temperature measurement method, several power cycling tests were performed on GaN HEMT from three different manufacturers. The main failure mechanism of the GaN HEMT from two manufacturers under power cycling tests is the degradation of solder layer between device and printed circuit board. The main failure mechanism of the devices from the third manufacturer is bond wire lift-off. In GaN the piezoelectric effect is involved in the formation of the 2DEG, and electrical characteristics are sensitive to compressive and tensile stress. The question is whether repetitive deformation leads to new failure mechanisms compared to Si devices.
Journal Article•10.1109/TIE.2018.2823662•
DC-Link Ripple Current Reduction Method for Three-Level Inverters With Optimal Switching Pattern

[...]

Seok-Min Kim1, In Jung Won, Juyong Kim2, Kyo-Beum Lee1•
Ajou University1, Korea Electric Power Corporation2
05 Apr 2018-IEEE Transactions on Industrial Electronics
TL;DR: This switching method is able to extend the lifetime of the dc-link capacitors by simple software programming and reduces the common-mode voltage and leakage current that represent high reliability and safety of the system.
Abstract: This paper presents an optimized switching strategy to reduce the dc-link ripple current for three-level photovoltaic (PV) inverters. The large electrolytic capacitors are commonly used for the dc link of power electronics applications to stabilize the dc-link voltage. The most important factor of designing the dc-link capacitor is the allowable current ripple. The over-ripple current flowing through the capacitor causes a high heat loss, shortened lifespan, low stability, and reliability. The proposed switching scheme selects voltage vectors and reconfigures dwelling order of the vectors to reduce the capacitor ripple current. This switching method is able to extend the lifetime of the dc-link capacitors by simple software programming. In addition, this switching method reduces the common-mode voltage and leakage current that represent high reliability and safety of the system. The effectiveness of the proposed method is verified with simulations and experimental results.
Proceedings Article•10.1109/ECTC.2018.00222•
Low Temperature Solder - A Breakthrough Technology for Surface Mounted Devices

[...]

Shubhada H. Sahasrabudhe1, Scott Mokler1, M. Renavikar1, Sandeep B. Sane1, Kevin Byrd1, Eric Brigham, Owen Jin, Pubudu Goonetilleke, Nilesh Badwe2, Satish Parupalli1 •
Intel1, Arizona State University2
1 May 2018
TL;DR: Low Temperature Solder for Surface Mounted Devices is introduced and its benefits to PC and electronic device manufacturers and Manufacturability and mechanical/ thermomechanical solder joint reliability data will be shared to demonstrate the impact of key technical modulators.
Abstract: Intel's commitment to the environment continues with a breakthrough technology – Low Temperature Solder for Surface Mounted Devices. In this paper we will introduce the technology and its benefits to PC and electronic device manufacturers. We will also discuss the process, material, design optimization efforts performed in order to ensure Yield, Quality and Reliability goals are met. Manufacturability and mechanical/ thermomechanical solder joint reliability data will be shared to demonstrate the impact of key technical modulators.
Journal Article•10.1002/ADMT.201800030•
A Transfer-Printed, Stretchable, and Reliable Strain Sensor Using PEDOT:PSS/Ag NW Hybrid Films Embedded into Elastomers

[...]

Xi Fan1, Naixiang Wang2, Feng Yan2, Jinzhao Wang3, Wei Song1, Ziyi Ge1 •
Chinese Academy of Sciences1, Hong Kong Polytechnic University2, Hubei University3
01 Jun 2018-Advanced materials and technologies
Abstract: Strain sensors can distinguish diverse deformations of target objects and have promising application as electronic skins, health monitors, soft robotics, etc. However, most of strain sensors suffer from reliability issue along with small strain‐sensing region due to the slippages of conducting components and the relaxation of their underlying elastomers. Here, a strain sensor with a sandwiched structure (i.e., poly(3,4‐ethylenedioxythiophene): poly(styrenesulfonate) and Ag nanowires (NWs) are embedded into polydimethylsiloxane) via a transfer‐printing technique is reported. The devices not only show a broad sensing region up to 50% strain with improved sensitivity, but also possess a reliable resistance response with recoverable conductance. The work provides a simple transfer‐printing method to make reliable, stretchable, and sensitive strain sensors for their promising implementation.
Development of a Signal-Free Intersection Control Logic in a Fully Connected and Autonomous Vehicle Environment

[...]

Amir Mirheli, Leila Hajibabai, Ali Hajbabaie
1 Jan 2018
TL;DR: A stochastic look-ahead technique is proposed based on Monte Carlo tree search algorithm to determine the near-optimal actions over time to prevent movement conflicts and significantly reduces travel time at intersections under various demand patterns.
Abstract: Abstract Establishment of effective cooperation between vehicles and transportation infrastructure improves travel reliability in urban transportation networks. Lack of collaboration, however, exacerbates congestion due mainly to frequent stops at signalized intersections. It is beneficial to develop a control logic that collects basic safety message from approaching connected and autonomous vehicles and guarantees efficient intersection operations with safe and incident free vehicle maneuvers. In this paper, a signal-head-free intersection control logic is formulated into a dynamic programming model that aims to maximize the intersection throughput. A stochastic look-ahead technique is proposed based on Monte Carlo tree search algorithm to determine the near-optimal actions (i.e., acceleration rates) over time to prevent movement conflicts. Our numerical results confirm that the proposed technique can solve the problem efficiently and addresses the consequences of existing traffic signals. The proposed approach, while completely avoids incidents at intersections, significantly reduces travel time (ranging between 59.4% and 83.7% when compared to fixed-time and fully-actuated control strategies) at intersections under various demand patterns.
Journal Article•10.1016/J.APENERGY.2018.02.006•
A unified multi-functional on-board EV charger for power-quality control in household networks

[...]

Seyedfoad Taghizadeh1, Md. Jahangir Hossain1, Junwei Lu, Wayne Water•
Macquarie University1
01 Apr 2018-Applied Energy
TL;DR: The proposed unified control system for a single-phase 4.5 kVA on-board multifunctional electric-vehicle (EV) charger that is connected to a low-voltage household network can enhance the building voltage profile, power quality, and reliability, which makes the proposed method a complete solution for low- voltage household networks.
Journal Article•10.1109/TIE.2018.2795568•
Reliability Improvement for a High-Power IGBT in Wind Energy Applications

[...]

Lina Alhmoud1•
Yarmouk University1
23 Jan 2018-IEEE Transactions on Industrial Electronics
TL;DR: A model integration is established in MATLAB/Simulink, which includes a doubly fed induction generator, an aerodynamic model, a drive train model, and a pitch control system, and the resulting reliability performance of the system has been significantly improved.
Abstract: The power command in wind energy conversion systems is subject to wind power fluctuations, which may cause significant thermal cyclings of high-power insulated-gate bipolar transistors and may, consequently, lead to a reduction in lifetime. To address this reliability issue, a model integration is established in MATLAB/Simulink, which includes a doubly fed induction generator (DFIG), an aerodynamic model, a drive train model, and a pitch control system. A detailed model of a three-phase converter is adopted for thermal modeling and lifetime estimation. A low-pass filter is utilized to improve the lifetime consumption of the rotor-side converter control in the active power loop in the DFIG. The simulation results indicate that the resulting reliability performance of the system has been significantly improved. Moreover, the capacity factor has been estimated.
Proceedings Article•10.1109/ECTC.2018.00251•
Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

[...]

Shuai Shao1, Yuling Niu1, Jing Wang1, Ruiyang Liu1, Seungbae Park1, Hohyung Lee1, Gamal Refai-Ahmed2, Laurene Yip2 •
Binghamton University1, Xilinx2
1 May 2018
TL;DR: In this article, a 2.5D Field-Programmable Gate Array (FPGA) assembly in both accelerated thermal cycling and power cycling was investigated by computational fluid dynamics (CFD) simulation and finite element analysis.
Abstract: 2.5D packages have been widely used in electronics industry for high performance and product miniaturization. As Through-Silicon-Via (TSV) fabrication methods and multi-level assembly technologies get mature, 2.5D packaging becomes reliable and affordable. In this work, board-level life prediction was performed for a 2.5D Field-Programmable Gate Array (FPGA) assembly in both accelerated thermal cycling and power cycling. Finite element models were built and validated by warpage measurement. Solder fatigue life in power cycling was investigated by computational fluid dynamics (CFD) simulation and finite element analysis. Improved life prediction for power cycling was achieved by mapping temperature results from CFD model to finite element model. Parametric studies regarding geometry and material factors were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. It is found that the designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.
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