Abstract: Microgrids are able to provide a coordinated integration of the increasing share of distributed generation (DG) units in the network. The primary control of the DG units is generally performed by droop-based control algorithms that avoid communication. The voltage-based droop (VBD) control is developed for islanded low-voltage microgrids with a high share of renewable energy sources. With VBD control, both dispatchable and less-dispatchable units will contribute in the power sharing and balancing. The priority for power changes is automatically set dependent on the terminal voltages. In this way, the renewables change their output power in more extreme voltage conditions compared to the dispatchable units, hence, only when necessary for the reliability of the network. This facilitates the integration of renewable units and improves the reliability of the network. This paper focusses on modifying the VBD control strategy to enable a smooth transition between the islanded and the grid-connected mode of the microgrid. The VBD control can operate in both modes. Therefore, for islanding, no specific measures are required. To reconnect the microgrid to the utility network, the modified VBD control synchronizes the voltage of a specified DG unit with the utility voltage. It is shown that this synchronization procedure significantly limits the switching transient and enables a smooth mode transfer.

Abstract: This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

Abstract: Today, micro-electronic circuits are undeniably and ubiquitously present in our society. Transportation vehicles such as cars, trains, buses, and airplanes make abundant use of electronic circuits to reduce energy consumption and emission of greenhouse gases and to increase passenger safety and travel comfort. Other products using electronic circuits are smartphones, tablet PCs, game consoles, household appliances, satellites, base stations, servers, etc. Each of these applications is becoming increasingly more complex to build. At the same time, the quality and reliability requirements for electronic circuits are more demanding than ever. To guarantee a high production yield and a sufficient circuit lifetime, possible hazards and failure effects have to be considered throughout the entire design flow. Such a flow includes the initial concept, the design itself, the testing of the prototype circuit, and finally the production process. The majority of integrated circuits manufactured today is processed in a complementary metal-oxide semiconductor (CMOS) technology. To reduce cost and to increase performance, the dimensions of all circuit components are shrinked with each new technology node. Associated with this technology scaling are the atomistic size of modern transistors, an increase of the gate-oxide electric field, and the introduction of new gate and channel materials. The combination of these elements results in an emerging reliability problem for advanced nanometer CMOS technologies. Transistor wearout manifests itself as a gradual and time-dependent shift of circuit characteristics which can result in circuit failure. Especially analog circuits, which are typically used as an interface between the real world and a digital backend, can be very sensitive to such small circuit parameter variations. This work focuses on the simulation and analysis of analog circuit reliability. The models and simulation techniques proposed in this dissertation are aimed to serve as an aid for circuit designers to better understand the impact of aging effects on their circuits and to enable the development of failure-resilient design solutions. In a first part of the work, an overview of all relevant nanometer CMOS unreliability effects is given and transistor compact models for the most important

Abstract: Resistive Random Access Memory (ReRAM) is one of the most promising emerging memory technologies as a potential replacement for DRAM memory and/or NAND Flash. Multi-level cell (MLC) ReRAM, which can store multiple bits in a single ReRAM cell, can further improve density and reduce cost-per-bit, and therefore has recently been investigated extensively. However, the majority of the prior studies on MLC ReRAM are at the device level. The design implications for MLC ReRAM at the circuit and system levels remain to be explored. This paper aim to provide the first comprehensive investigation of the design trade-offs involved in MLC ReRAM. Our study indicates that different resistance allocation schemes, programming strategies, peripheral designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM design against MLC phase-change memory (PCM) and multi-layer cross-point ReRAM design, and point out why multi-level ReRAM is appealing; second we further explore the design space for MLC ReRAM.

Abstract: Voltage noise not only detracts from reliability and performance, but has been used to attack system security. Most systems are completely unaware of fluctuations occurring on nanosecond time scales. This paper quantifies the threat to FPGA-based systems and presents a solution approach. Novel measurements of transients on 28nm FPGAs show that extreme activity in the fabric can cause enormous undershoot and overshoot, more than 10× larger than what is allowed by the specification. An existing voltage sensor is evaluated and shown to be insufficient. Lastly, a sensor design using reconfigurable logic is presented; its time-to-digital converter enables sample rates 500× faster than the 28nm Xilinx ADC. This enables quick characterization of transients that would normally go undetected, thereby providing potentially useful data for system optimization and helping to defend against supply voltage attacks.

Abstract: Due to the increasing security and reliability demand of actual industrial process control systems, the study on fault diagnosis and fault tolerant control of dynamic systems has received considerable

Abstract: Preface Part 1: Materials Issues and Reliability of Optical Devices 1. Reliability Testing of Semiconductor Optical Devices 2. Failure Analysis of Semiconductor Optical Devices 3. Failure Analysis using Optical Evaluation Technique (OBIC) of LDs and APDs for Fiber Optical Communication 4. Reliability and Degradation of III-V Optical Devices Focusing on Gradual Degradation 5. Catastrophic Optical-damage in High Power, Broad-Area Laser-diodes 6. Reliability and Degradation of Vertical Cavity Surface Emitting Lasers 7. Structural Defects in GaN-based Materials and Their Relation to GaN-based Laser Diodes 8. InGaN Laser Diode Degradation 9. Radiation-enhanced Dislocation Glide - The Current Status of Research 10. Mechanism of Defect Reactions in Semiconductors Part 2: Materials Issues and Reliability of Electron Devices 11. Reliability Studies in the Real World 12. Strain Effects in AlGaN/GaN HEMTs 13. Reliability Issues in AlGaN/GaN High Electron Mobility Transistors 14. GaAs Device Reliability: High Electron Mobility Transistors and Heterojunction Bipolar Transistors 15. Novel Dielectrics for GaN Device Passivation And Improved Reliability 16. Reliability Simulation 17. The Analysis of Wide Bandgap Semiconductors Using Raman Spectroscopy 18. Reliability Study of InP-Based HBTs Operating at High Current Density Index

Abstract: This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

Abstract: Insulated Gate Bipolar Transistors (IGBTs) are key component in power converters. Reliability of power converters depend on wear-out process of power modules. A physical parameter such as the on-state collector-emitter voltage (Vce) shows the status of degradation of the IGBT after a certain cycles of operation. However, the Vce mainly shows the wear-out of bond wire lift-off and solder degradation. The Vce is normally used to estimate the junction temperature in the module. The measurement of Vce is sensitive to the converter power level and fluctuations in the surrounding temperature. In spite of difficulties in the measurement, the offline and online Vce measurement topologies are implemented to study the reliability of the power converters. This paper presents a review in wear-out prediction methods of IGBT power modules and freewheeling diodes based on the real time Vce measurement. The measurement quality and some practical issues of those measurement techniques are discussed. Furthermore, the paper proposes the requirements for the measurement and prognostic approach to determine wear-out status of power modules in field applications. The online Vce measurement for a selected topology is also shown in the paper.

Abstract: The use of renewable energy sources has increased year-on-year. Thus, there is an increasing rate of small generating units connected directly to distribution networks and micro-grids close to consumers. At the same time, these micro-sources must provide stability and reliability of electrical energy to the power network to which they are connected. In the technical literature, several studies have been done to ensure power systems with traditional generating sources to operate in a stable and reliable way, but there is an issue regarding generation uncertainty when a distribution system has many micro-sources. This is because of the uncertainty of primary sources, for example, wind and radiation intensity, and could result in intermittent generation. In this study, stability and reliability of voltage in a power system with distributed generation is analysed using simulation techniques. In the proposed method in this study voltage security analysis is jointly considered with probability laws. Moreover reliability theory is also considered in the proposed voltage collapse analysis methodology. The responsibility of generator in the voltage collapse process, the probabilistic risk of voltage collapse of each operating point and the probability of enlarging the system load as a function of different operating points are the outcome of the methodology, and it is validated by using the IEEE34 test feeder.

Abstract: Unbalanced grid voltage causes a large second-order harmonic current in the dc-link capacitors as well as dc-voltage fluctuation, which potentially will degrade the lifespan and reliability of the capacitors in voltage source converters. This paper proposes a novel dc-capacitor current control method for a grid-side converter (GSC) to eliminate the negative impact of unbalanced grid voltage on the dc-capacitors. In this method, a dc-capacitor current control loop, where a negative-sequence resonant controller is used to increase the loop gain, is added to the conventional GSC current control loop. The rejection capability to the unbalanced grid voltage and the stability of the proposed control system are discussed. The second-order harmonic current in the dc capacitor as well as dc-voltage fluctuation is very well eliminated. Hence, the dc capacitors will be more reliable under unbalanced grid voltage conditions. A modular implementation method of the proposed control strategy is developed for the DFIG controller. Finally, experiments are presented to validate the theoretical analysis.

Abstract: This article starts from the same points that generated the John Tanaka review, as an homage to his unforgettable contribution to the science of dielectrics and electrical insulation.

Abstract: A k-out-of-n:G system consists of n components, and operates if at least k of its components operate. Its reliability properties have been widely studied in the literature from different perspectives. This paper is concerned with the reliability analysis of a k-out-of-n:G system equipped with a single warm standby unit. We obtain an explicit expression for the reliability function of the system for arbitrary lifetime distributions. Two different mean residual life functions are also studied for the system.

Abstract: Power density and reliability specifications for motor drives in traction applications are getting increasingly stringent. The main challenge in meeting these conflicting requirements, is managing heat dissipation. A drive's peak torque rating is limited by switching device temperatures which must be kept below critical values at all times for the sake of reliability, preferably without major hardware adaptations. In this challenge lies a large potential for advanced control algorithms. This paper proposes a PMSM drive control strategy which combines active thermal management with dynamic DC-link voltage adaptation. The bus voltage level is adjusted to the required PMSM terminal voltage in each operating point. Doing so, switching losses can be reduced at low speed by lowering the bus voltage. At high speed, the voltage level is boosted and field-weakening operation and the associated additional losses are avoided. An 11 kW PMSM drive, with an active front-end controlling the bus voltage, is used as a test setup to mimic a series-hybrid drivetrain. Compared to a fixed DC-link voltage, efficiency maps show a significant inverter loss reduction at low speed. This results in lower switching device temperatures which in turn allows a higher peak torque rating.

Abstract: TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. The stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method (FEM) was used to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Fatigue failures of the C4 and BGA joints are the two primary reliability focuses in the present study. Experimental data collected on the CoWoS™-enabled test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme. The results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid, and when the Tg of the underfill of C4 bump is higher, the C4 bump has better reliability. Furthermore, 3D thermo-mechanical and reliability study of BGA balls is presented for organic and ceramic substrates. Several DOEs have been constructed for ceramic substrate to increase BGA reliability by optimizing C4 underfill material and package design. The effect of board layer count and design is detailed. Finally reliability of BGA balls, C4 and micro-bumps are compared for a part that is mounted on a PCB board.

Abstract: The thermal management is a crucial design problem for mobile devices because it greatly affects not only the device reliability, but also the leakage energy consumption. Conventional dynamic thermal management (DTM) techniques work well for the computer systems. However, due to the limitation of the physical space in mobile devices, the thermal coupling effect between the major heat generation components, such as the application processor (AP) and the battery, plays an important role in determining the temperature inside the mobile device package. Due to this effect, the thermal behavior of one part is no longer independent of the other, but is affected by the temperature of other parts. This is the first work that quantitatively characterizes the thermal coupling between the battery and AP and presents a predictive DTM for mobile devices considering this effect. Simulation results show that the proposed DTM method significantly reduces the thermal violations for the target mobile devices.

Abstract: With the size of transistors scaling down, 3D IC packaging emerged as one of the most promising solutions to achieve system integration on the track of Moore's Law. In this article, we demonstrated a sub-system with one 28nm logic device and two 40nm chips on a 600mm2 silicon interposer with Through-Silicon-Via (TSV) integrating 4 layers of high density interconnects. The packages were assembled using our proprietary CoWoS (Chip on Wafer on Substrate) technology that incorporated 270,000 micro-bump (μBump) and 8,700 C4 bumps. Comprehensive reliability characterization and test methods will be presented. It includes copper interconnect reliability of silicon interposer on EM, SM and IMD TDDB with the presence of TSV. μBump EM and TSV EM are characterized to provide a design guideline for maximum current carrying capability; the EM test methodology was also used to optimize the integrated process, e.g. TSV copper plating, μBump joint, and interface treatment of TSV revealing. Package process optimization, bill of material selectio n and qualificatio n we r e conducted on a 28nm Cu/ELK (Extreme low-K) test vehicle taking Chip-Package-Interaction into consideration. Not only component level package reliability tests were performed, board level Thermal Cycling, Power Cycling and Mechanical Shock tests were also executed to understand the reliability margin and potential failure modes in field use condition. The typical failure modes and mechanisms will be discussed. CoWoS technology is eventually successfully developed with enhanced reliability. The results highlight the importance of a highly integrated 3D IC technology from silicon wafer process to assembly packaging. This work shows that in the new paradigm of 3D IC integration, Si Foundry is positioned at a unique leadership to manage the innovation in Si processes and the improvement of Si assembly operating life.

Abstract: With the trend toward more electrical aircraft, Silicon Carbide power switches could be heavily used for high temperatures applications within the aircraft. The assessment of the reliability of such power electronic components is a key element for the qualification process. In this study we focused on the reliability of the MOSFET gate oxide which is known to be the more fragile part of these components.

Abstract: This paper discusses issues related to reliability of uninterruptible power supplies equipped with automatic protection mechanisms (short circuit protection – SCP, overload protection – OLP, overvoltage protection – OVP) Relationships for determining probability of system states: full operational capability, partial capability and failure were derived The impact of time taken to restore the state of full operational capability on probability of different system states was also analysed

Abstract: Diode laser fundamentals are discussed, followed by an elaborate discussion of problem-oriented design guidelines and techniques, and by a systematic treatment of the origins of laser degradation and a thorough exploration of the engineering means to enhance the optical strength of the laser. Stability criteria of critical laser characteristics and key laser robustness factors are discussed along with clear design considerations in the context of reliability engineering approaches and models, and typical programs for reliability tests and laser product qualifications. Novel, advanced diagnostic methods are reviewed to discuss, for the first time in detail in book literature, performanceand reliability-impacting factors such as temperature, stress and material instabilities.

Abstract: Wafer fusion vertical cavity surface emitting laser (VCSEL) technology has produced devices that successfully passed all mechanical and electrical Telcordia qualification tests. Accelerated lifetime tests result in times to 1% failure at 70 $^{\circ}{\rm C}$ of 18 years and 30 years at VCSEL driving currents of 9 and 8 mA, respectively. These lifetimes meet the telecom industry reliability requirements for applications in fiber-optic communications networks.

Abstract: Reactive power plays a significant role in power system operation. However, in reliability evaluation, attention has seldom been paid to reactive power. In conventional power system reliability evaluations, the fixed maximum and minimum values are applied as the reactive power limits of generators. Failures of reactive power sources are rarely considered. The detailed causes of network violations for a contingency are also seldom studied. Real power load shedding is usually used to alleviate network violations without considering the role of reactive power. There are no corresponding reliability indices defined to represent the reactive power shortage in the existing techniques. Reactive power shortage and the associated voltage violations due to the failures of reactive power sources are considered in this paper. New reliability indices are proposed to represent the effect of reactive power shortage on system reliability. The reliability indices due to reactive power shortages have been defined and are separated with those due to real power shortages. Reactive power limits determined by real power output of a generator using curve have been studied. A reactive power injection technique is proposed to determine possible reactive power shortage and location. The IEEE 30-bus system has been modified and analyzed to illustrate the proposed technique. The results provide system planners and operators very important information for real and reactive power management.

Abstract: A low cost system for measuring soil water potential and data logging was developed on the basis of an Arduino microcontroller board, electronic pressure transducers and water-filled tensiometers. The assembly of this system requires only minimal soldering, limited to the wiring of the power supply and the pressure sensors to the microcontroller board. The system presented here is, therefore, not only inexpensive, but also suited for easy reproduction by users with only basic technical skills. The utility and reliability of the system was tested in a commercial apple orchard.

Abstract: A forming-free SiN-based resistive switching memory (RSM) device has been successfully realized using an RF sputtering method. With a 10-nm thick SiN film, the memory device showed forming-free switching behavior under ±2 V/100 ns. The conduction mechanisms at low- and high-resistance states were verified by Ohmic behavior and modified space-charge-limited conduction, respectively. In a reliability test, the device exhibits good endurance over 109 cycles and long data retention over 105 s at 85 °C. These results demonstrate that SiN-based RSM devices can be readily available without forming processes using an RF sputtering method.

Abstract: In general, power converters are being operated in closed-loop systems, and any characteristic variations in one component will simultaneously alter the operating point of other components resulting in a shift in overall reliability profile. This interdependence makes the reliability of a converter a complex function of time and operating conditions; and therefore, the application may demand periodic replacement of converters to avoid downtime and maintenance cost. By knowing the present state of health and remaining life of a power converter, it is possible to reduce the maintenance cost for expensive high-power converters. This paper presents a reliability analysis for a boost converter although this method could be used to any power converter being operated in closed-loops. Through the conducted study it is revealed that the reliability of a boost converter with control loops degrades with time, and this paper presents a method to calculate time varying reliability of a boost converter as function of characteristic variations in different components in the circuit. In addition, the effects of operating and ambient conditions have been included in the reliability model as well. It was found that any increase in the ON-resistance of the MOSFET or equivalent series resistance (ESR) of the output capacitor decreases the overall reliability of the converter. However, any variation in the capacitance has more complex impact on the converter's reliability. This conducted research is a step forward to the power converter reliability analysis because the cumulative effect of multiple degraded components has been considered in the reliability model.