Abstract: Electrostatic-driven microelectromechanical systems devices, in most cases, consist of couplings of such energy domains as electromechanics, optical electricity, thermoelectricity, and electromagnetism. Their nonlinear working state makes their analysis complex and complicated. This article introduces the physical model of pull-in voltage, dynamic characteristic analysis, air damping effect, reliability, numerical modeling method, and application of electrostatic-driven MEMS devices.

Abstract: Modern digital IC designs have a critical operating point, or “wall of slack”, that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. We propose a design-level approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. We increase the range of voltage values at which the (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner. The resulting designs heuristically minimize the voltage at which the maximum allowable error rate is encountered, thus minimizing power consumption for a prescribed maximum error rate and allowing the design to fail more gracefully. Compared with baseline designs, we achieve a maximum of 32.8% and an average of 12.5% power reduction at an error rate of 2%. The area overhead of our techniques, as evaluated through physical implementation (synthesis, placement and routing), is no more than 2.7%.

Abstract: This letter describes an analytical approach to determining the size, in terms of both power and energy capacity, of a backup storage unit in such a way as to meet a specified reliability target. The backup could be in the form of electrical energy storage or fuel storage. The proposed approach might benefit facilities that require high levels of reliability in their electric supply.

Abstract: CMOS circuits operating up to 60GHz have been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1–6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal operation. Moreover, Class-A or Class-AB power amplifiers (PA) are mandatory to overcome the difficulty of the limited maximum available gain (MAG) at mm-Wave frequencies [1–6] and the high linearity required by the OFDM modulation used in the IEEE 802.15.3c wireless HD standard. That means a maximum drain-source voltage swing of twice the DC voltage, which introduces specific design or supply voltage in order to respect reliability constraints [1,7]. This paper describes a PA with 8 power-combined ways and cascode topology in a 7-metal-layer 65nm CMOS process which covers the full band for 60GHz wireless applications. The presented circuit operates at a standard supply of 1.2V or 1.8V, and achieves a saturated output power of 16.6dBm and 18.1dBm respectively. The measured output power is high for CMOS while insuring reliability for time-dependent dielectric breakdown (TDDB) and hot-carrier-injection (HCI) degradation.

Abstract: In this paper, we introduce the notion of process reliability based trojans which reduce the reliability of integrated circuits through malicious alterations of the manufacturing process conditions. In contrast to hardware/software trojans which either alter the circuitry or functionality of the IC respectively, the process reliability trojans appear as a result of alterations in the fabrication process steps. The reduction in reliability is caused by acceleration of the wearing out mechanisms for CMOS transistors, such as Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI). The minor manufacturing process changes can result in creation of infected ICs with a much shorter lifetime that are difficult to detect. Such infected ICs fail prematurely and might lead to catastrophic consequences. The paper describes possible process alterations for both NBTI and HCI mechanisms that might result in creation of process reliability trojans. The paper also explores some possible detection techniques that can help identify the hidden trojans and discusses the various scenarios when process reliability based trojans lead to severe damages.

Abstract: This paper discusses various aspects of unified power flow controller (UPFC) control modes and settings and evaluates their impacts on the power system reliability. UPFC is the most versatile flexible ac transmission system device ever applied to improve the power system operation and delivery. It can control various power system parameters, such as bus voltages and line flows. The impact of UPFC control modes and settings on the power system reliability has not been addressed sufficiently yet. A power injection model is used to represent UPFC and a comprehensive method is proposed to select the optimal UPFC control mode and settings. The proposed method applies the results of a contingency screening study to estimate the remedial action cost (RAC) associated with control modes and settings and finds the optimal control for improving the system reliability by solving a mixed-integer nonlinear optimization problem. The proposed method is applied to a test system in this paper and the UPFC performance is analyzed in detail.

Abstract: This paper proposes a dynamic electrothermal model that can be simulated with the power electronic circuit simulator. It includes a temperature-dependent loss calculation of power semiconductor devices. The proposed model is used to estimate the transient junction temperature of the semiconductor devices. In so doing, the resulting junction temperature is used to facilitate the power sharing between parallel-connected converters. The use of power-cycling method based on junction temperature helps in increasing the over all system efficiency and reliability of the system. This part of the paper focuses on the method of thermal modeling and discusses how the model can be used for different converters, modulation techniques, and devices.

Abstract: The following paper will give an overview about the main reliability aspects of silicon carbide power devices. After a brief review of the key device concepts it covers reliability topics of bipolar devices, Schottky diodes, metal oxide semiconductor field effect devices, and junction field effect devices. Special attention is paid to the influence of the different reliability topics on the commercialization of the different device types. It will be shown that for some device types the reliability is at a very high level being not hampering commercialization (e.g. Schottky diodes or junction field effect devices) whereas other devices concepts still need improvement until commercialization (e.g. bipolar devices).

Abstract: Responsive load is still the most underutilized reliability resource in North America. This paper examines the characteristics of concern to the power system, the renewables, and to the loads.

Abstract: The use of high-end multicore processors today can incur high power density with significant variability in spatial and temporal usage of resources by workloads. This situation leads to power and temperature hotspots, which in turn may lead to non-uniform ageing and accelerated chip failure. These drawbacks can be mitigated by online tuning of system performance and adopting closed-loop thermal and reliability management policies. The development and evaluation of these policies cannot be performed solely on real hardware - due to observability and flexibility limitations or just by relying on trace-driven simulation, due to dependencies present among power, thermal effects, reliability and performance. We present a complete and virtual platform to develop, simulate and evaluate power, temperature and reliability management control strategies for high-performance multicores. The accuracy and effectiveness of our solution are ensured by integrating a established system simulator (Simics) with models for power consumption, temperature distribution and aging. The models are based on characterization on real hardware. Control strategies exploration and design are carried out in the MATLAB/Simulink framework allowing the use of control theory tools. Fast prototyping is achieved by developing a suitable interface between Simics and MATLAB/Simulink, enabling co-simulation of hardware platforms and controllers.

Abstract: Thermal spray in general, plasma spray in particular, is a highly complex process with numerous interacting variables associated with generation of the spray stream, deposit formation dynamics, and the resultant property linkages. Compounding this variability further are both the spatial (different booths and different locations) and temporal (process start-stops, hardware degradation, operator etc.) effects. As such, an understanding of process and coating consistency and variability offers significant challenges. Recent scientific advances as well as measurement tools have enabled elucidation of the intrinsic variabilities associated with each of the process sub-steps; however, integrated understanding of the system level reliability is still lacking. This article seeks an integrated assessment of process and coating reliability through systematic measurements of variabilities during each stage of the process subjected to different operating parameters. Through critical examination of first-order process maps, the influence of process parameters on particle state is reviewed for repeated spray runs with a single parameter effect as well as across a spectrum of process parameters. In addition, influence of these changes on design-relevant coating properties were obtained for plasma-sprayed zirconia through recourse to novel in situ and ex situ substrate curvature measurements. Finally, the implications of such integrated reliability studies have been explored through collaborative experiments conducted in the industrial sites.

Abstract: High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction of new materials and requirement of higher field of operation for higher performance. In this paper, key and unique HK+MG intrinsic transistor reliability mechanisms observed on 32nm logic technology generation is presented. We'll present intrinsic reliability similar to or better than 45nm generation.

Abstract: In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.

Abstract: A custom multi-chip power module packaging was designed to exploit the electrical and thermal performance potential of silicon carbide MOSFETs and JBS diodes. The dual thermo-mechanical package design was based on an aggressive 200°C ambient environmental requirement and 1200 V blocking and 100 A conduction ratings. A novel baseplate-free module design minimizes thermal impedance and the associated device junction temperature rise. In addition, the design incorporates a free-floating substrate configuration to minimize thermal expansion coefficient induced stresses between the substrate and case. Details of the module design and materials selection process will be discussed in addition to highlighting deficiencies in current packaging materials technologies when attempting to achieve high thermal cycle life reliability over an extended temperature range.

Abstract: Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This tutorial provides the fundamental and advanced knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during manufacturing test. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low-power design techniques and shows how low-power circuits and systems can be tested safely without affecting yield and reliability. Electronic Design Automation (EDA) solutions for testing low-power devices are also covered in the last part of the tutorial.

Abstract: Thermal design is an important condition for electron-equipment's reliability Introduce thermodynamic theory about elimination of heat,expound the basic steps of thermal design from how to choose the technique about elimination of heat and the element layout in detail,discuss some new technique and methods about elimination of heat The theory and experience from practice about thermal design have important assistant effect in configuration design

Abstract: The concept of a "More Electric Aircraft" (MEA) leads, among other actions, to the substitution of hydraulic-based actuators for Electro-Mechanical Actuators (EMA). Removal of the engine hydraulic pumps requires fully-operative electrical power actuators and mastery of the flight control architecture. However, unexpected faults and lack of safety hinder the massive use of EMAs in flight control actuators and force the development of new systems and methods for supervision in aircrafts actuators. On-line supervision of the motor drive, by means of electrical signature and harmonics analysis, can detect motor faults in its most preliminary state, thus allowing increasing the EMA reliability. However, for typical non-stationary conditions in EMA operation, classical Fourier transform cannot be applied, and other time-frequency decompositions must be explored. This presents an application of Discrete Wavelet Transform to electrical and mechanical Permanent Magnet Synchronous Motor fault detection. Experimental results are shown and prove that affordable Predictive Testing and Inspection technologies can be used to assure the reliability of the new EMAs.

Abstract: GaN-based heterojunction field effect transistors (HFETs) will play major roles in the high-power, high-frequency military and commercial arenas for microwave and millimeter wave transmitters and receivers used in communications and radar devices. In fact, devices operative in the X-band (7-12.5 GHz) and beyond are already at market and boast quite impressive performances. Having improved the crystal quality now to levels where the reliability (expressed as mean time to failure (MTTF)) is claimed to exceed ten million hours, the work now needs to focus on which of the physical mechanisms responsible for degradation are the most important, and how the existing degradation accelerates subsequent degradation, ultimately resulting in device failure. Available data show that not all devices from the same wafer show similar longevity and the wide spread of activation energies reported for three- temperature extrapolation-based predictions of the lifetime are troubling. If we hope to make consistent, reliable predic- tions of device lifetimes, particularly when the devices are being pushed in radio-frequency (RF) operation to near their limits, more work will need to be done in characterizing the long term stability of the devices, and new physical models for the failure mechanisms will have to be developed.

Abstract: According to the International Technology Roadmap for Semiconductors (ITRS), embedded Static Random Access Memory (SRAM) will continue to dominate the area of System on Chips (SoCs) approaching 90% in the next 10 years. Therefore, SRAM reliability will have a significant impact on overall SoC reliability. This paper presents state-of-the-art transistor failure mechanisms and their impact on SRAM reliability parameters including cell stability, cell read failures, and cell access time failures. Furthermore, different techniques currently employed in industry, to mitigate the impacts of the failure mechanisms are presented. Finally, based on the current scaling trends reliability challenges of future transistors and embedded SRAM are discussed. The discussion concludes that the reliability challenges in future embedded SRAM will increase significantly.

Abstract: Objective: To ascertain the extent to which the new microelectronic sensors Smart Retainer® and TheraMon® are suitable for measuring wear times in orthodontic treatment. Materials and Methods: The Smart Retainer® wear-time sensor and a prototype of the TheraMon® microsensor were each polymerized into upper plates. The orthodontic appliances were exposed to periodically altered temperatures in a thermostatic water bath. Results: The wear-time sensors recorded the changes in water temperatures as “wear time” (~35 °C) or “non-wear time” (room temperature). The wear times stored in the sensors were displayed and printed outside the water bath as “wear-time graphs” via readout stations and computers. To be better able to predict their reliability and applicability in orthodontic treatment, we measured the accuracy of the two wear-time sensors by comparing the wear times recorded by the Smart Retainer® and TheraMon® with the programmed water temperatures. Conclusion: Both microelectronic sensors fulfilled the basic requirements for use as objective wear-time sensors in orthodontic appliances in clinical trials and routine orthodontic practice. As it can be incorporated into different orthodontic appliances, the smaller TheraMon® system offers greater versatility than the Smart Retainer®. The TheraMon® also permits the accurate documentation and analysis of wear times down to the minute.

Abstract: In this paper we give a brief historical review of the evolution of device reliability research over the past decades. Then we give some examples on how established characterization techniques that were developed for silicon based devices can be completely misinterpreted when applied to Ge or III–V based MOS-structures, and how a simple modification of the technique can ensure a correct interpretation. We also show how novel techniques, such as TSCIS (Trap spectroscopy by Charge Injection and Sensing). were developed recently to overcome the problem of dielectric material screening for logic and memory applications. With the scaling of the devices into the nanometer regime single traps are causing large variations in the device parameters, which leads to a time-dependent variability, which makes lifetime analysis difficult. Finally we show that when using the classical reliability assessment methodology based on accelerated testing, the available reliability margins are strongly reduced, in some cases even down to zero, especially for sub-1nm EOT (Effective Oxide Thickness) devices. As a result, we argue that the reliability community will have to look for alternative ways to ensure and guarantee the lifetime of future products.

Abstract: This paper proposes the performance improvement method for the voltage-fed continuous input current quasi-impedance source inverter (qZSI) by the introduction of the two-stage quasi-Z-source network (qZS-network). The two-stage qZS is derived by the adding of one diode, one inductor and two capacitors to the traditional qZSI. The proposed two-stage qZSI inherits all the advantages of traditional solution (voltage boost and buck functions in a single stage, continuous input current and improved reliability). Moreover, the proposed solution features over the 30% shoot-through duty cycle reduction for the same voltage boost factor and component stresses as compared to conventional qZSI. Theoretical analysis of the two-stage qZSI in shoot-through and non-shoot-through operating modes is presented. The design guidelines for the two-stage qZS-network based step-up DC/DC converter are provided. A prototype has been built to verify the theoretical assumptions. The simulation and experimental results are presented and discussed.

Abstract: Distributed power systems are getting more attention now-a-days due to their high flexibility and reliability. In this paper, predictive current control strategy is proposed for the grid-connected four-leg inverters. This kind of converter is developed to deliver power to the unbalanced/nonlinear three-phase loads and as well to the grid. The discrete-time model of the converter and load is used to predict the future behavior of the load currents for each valid switching state. The control method chooses a switching state that minimizes the error between the output currents and their references. The feasibility of the proposed method is verified by computer simulations, showing a good performance and capacity to compensate the disturbances.