Abstract: The paper proposes a procedure for life estimation of high voltage AC cables in real operating conditions, i.e. subjected to voltage and load cycles, so that electrothermal stress is the dominant aging factor of cable insulation. As possible alternatives for representing the effects of the electrothermal aging of insulation, three life models wellknown in literature are considered, namely the Zurkov, Crine and Arrhenius-IPM models, each within the probabilistic framework needed for associating time-to-failure with reliability. The cumulation of loss-of-life fractions over load cycles is evaluated through Miner's law. The thermal transients that affect insulation as a consequence of cyclic current variations are simulated via the CIGRE two-loop thermal network analog. The procedure is applied to XLPE-insulated high voltage AC cables, subjected to two typical stepwise-constant daily load cycles differing as to the load severity. The application shows that cable life is very sensitive to load cycles, thermal transients and electrothermal synergism, aspects that all deserve attention for estimating accurately the life expectancy of high voltage AC cables in service. The three life models employed, though weighing differently the electrothermal synergism as a consequence of their own functional expressions, give a concordant indication about the possible life extension of cables already in service.

Abstract: A questionnaire survey was carried out to determine the industrial requirements and expectations of reliability in power electronic converters. According to the survey, power semiconductor devices ranked the most fragile components. It was concluded that main stresses were from the environment, transients and heavy loads, which should be considered during power electronic system design and normal operation. Further analyses suggest that power device reliability is a key issue and power electronic converter design is correlated with failure costs.

Abstract: An on-chip reliability monitor capable of separating the aging effects of HCI, BTI, and TDDB with sub-ps precision is presented. A pair of stressed ring oscillators is implemented in which one ages due to both BTI and HCI, while the other suffers from only BTI. Frequency degradation is monitored with a beat frequency detection system achieving sub-μ s measurement times. Measurement results are presented from a 65nm test chip over a range of stress conditions.

Abstract: In order to ensure increasing current rating of semiconductor switches, paralleling is unavoidable. In this paper, the paralleling of switches has been studied from the reliability point of view. A prototype 4-kW boost converter has been used for this paper. In this boost converter, five insulated gate bipolar transistors are paralleled per switch in order to increase the current rating. Based on experimental results, the reliability of converter has been calculated. Results of reliability calculations showed that paralleling switches extremely decreases reliability of DC-DC converters. The same converter has been constructed by using an integrated power module (IPM). The same calculations have been repeated for the IPM-based converter. The comparison of the results shows that the case of IPM in converters can increase the reliability of the circuit.

Abstract: a general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation

Abstract: Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations.

Abstract: In this review, essential topics on reliability characterization of plasma-induced damage are discussed. First, the basic degradation of a metal-oxide-semiconductor (MOS) gate oxide from plasma processing steps is described. Second, the reliability characterization techniques and basics are discussed and problem areas are highlighted. Discussion points include the antenna ratio definition, test structure layout employing MOS transitors with and without antennas, stress and measurement sequence including a revealing stress, use of protection elements against plasma-charging, plasma-charging effects on metal-insulator-metal capacitors, and plasma-charging effects on high-k dielectrics of field-effect transistors.

Abstract: A program is underway at Sandia National Laboratories1 to predict long-term reliability of photovoltaic systems. The vehicle for the reliability predictions is a Reliability Block Diagram (RBD), which models system behavior. Because this model is based mainly on field failure and repair times, it cannot currently be used to accurately predict end-of-life. In order to be truly predictive, physics-informed degradation processes and failure mechanisms need to be included in the model. This paper describes accelerated life testing of metal foil tapes used in thin-film PV modules, and how tape joint degradation, a possible failure mode, can be incorporated into the model.

Abstract: This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve reliable 3D EMWLP. Several molding process issues, such as warpage, die-sweep, EMC penetration, and die-shift, were faced during embedding process development. A large warpage of more than 1 mm and die-shift of more than 600 µm were found to occur in reconstructed molded wafer. Wafer level embedding process was optimized to reduce warpage and die-shift problems. A significant reduction in warpage (∼ 30 %) and die-shift (∼ 88 %) were achieved after embedding process optimization. The detail of process optimization is presented in the paper. Reconstructed molded wafers were subjected to various reliability tests, such as thermal cycle (TC), moisture sensitivity test-level 3 (MST-L3), and highly accelerated stress test (HAST). Scanning acoustic microscopy (SAM) analysis of molded wafers was carried out to analyze the void formation and delamination in molded wafers. No major void or delamination was observed in reconstructed wafer after molding as well as after reliability tests.

Abstract: This paper examines the performance and reliability implications associated with aggressively biased cascode SiGe HBT power-amplifier cores under large-signal RF operating conditions. The role of high-power RF stress on device degradation and failure is examined in detail. General expressions for a large-signal RF safe-operating area, which account for the effect of load impedance on the dynamic output current and voltage characteristics, are presented. These show excellent agreement with experimental results. Useful operating guidelines for reliable large-signal operation are provided.

Abstract: In this paper, we describe highly reliable GaN high electron mobility transistors (HEMTs) for high-power and high-efficiency amplifiers. First, we present the reliability mechanisms and progress on the previously reported GaN HEMTs. Next, we introduce our specific device structure for GaN HEMTs for improving reliability. An n-GaN cap and optimized buffer layer are used to realize high efficiency and high reliability by suppressing current collapse and quiescent current (I dsq )-drift. Finally, we propose a new device process around the gate electrode for further improvement of reliability. Preventing gate edge silicidation leads to reduced gate leakage current and suppression of initial degradation in a DC-stress test under high-temperature and high-voltage conditions. Gate edge engineering plays a key role in reducing the gate leakage current and improving reliability.

Abstract: An LVDC (low voltage DC) distribution system is a promising technology to be used in future smart distribution system having high level cost-efficiency and reliability. Protection of an LVDC distribution system differs from the traditional 20/0.4 kV AC distribution network; direct current and IT network complicates the customer-end protection. This paper describes practical protection solutions for the LVDC network and presents an LVDC system laboratory prototype in which experimental testing is performed.

Abstract: The Schottky contact on GaN HEMT power devices is a key element for high power performance and its long term reliability behavior. Up to now such GaN devices are still suffering very often by a leakage current increase during operation resulting in deteriorated transistor behavior. One reason for this problem is owing to insufficiently stable Schottky contacts based on NiAu metalisation. We analysed GaN HEMTs with different aging behaviors by means of HR-TEM and EDX investigations. It could be shown that on transistors with increasing leakage current Au was found directly on the Schottky interface which may be responsible for the increase of the leakage current. Furthermore, there are strong indications that such Au is diffusing via the gate foot side wall Ni-SiN interface towards the Schottky barrier. It is proposed that an additional metallic diffusion barrier may solve this aging problem. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Abstract: In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.

Abstract: One of the major sources of losses in a photovoltaic (PV) system is the mismatch between the amounts of energy generated by two or more modules inside an array. This mismatch can be caused for instance by partial shading of the modules. This paper investigates the performance decrease of PV-modules under non-optimal irradiance conditions, and also some techniques used to mitigate this problem. Firstly, mathematical modeling of the PV module is simulated under different level of shading. Performance comparison is done between PV string configuration and those based on module level MPP tracking units in terms of mismatch losses. Further, promising technologies which increase the efficiency and reliability of such systems under mismatch conditions such as active bypass, AC-Modules and power optimizers are discussed.

Abstract: There still remain a number of reliability problems to be resolved with regard to long-term high junction temperature operation of SiC power devices because at present they simply follow Si-based technology. In this paper, various reliability issues for power DMOS devices on 4H-SiC operated at a junction temperature of more than 200 °C are extensively discussed in terms of five manifest problems and potential treats: (1) interlayer dielectric erosion, (2) Al spearing, (3) Ni2Si contact disappearance, (4) electrode delamination, and (5) gate time-dependent dielectric breakdown. Preventive measures for these issues are proposed, including the use of a Ta/TaN barrier metal, a SiCH barrier dielectric, decarbonised Ni2Si and an ONO gate dielectric, and their effectiveness is experimentally verified. A viable device structure and fabrication process that successfully incorporate these measures are then presented. Finally, a storage life of more than 5380 hours at 300 °C is demonstrated for 1 × 1 mm2 4H-SiC power DMOS devices incorporating selected countermeasures. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Abstract: This paper discusses methods for quantifying the performance of microgrids during island operation. Such methods are essential for comparing different designs and different control algorithms. Performance indicators and objectives are proposed for voltage-quality variations, for individual dips and interruptions, and for the reliability during island operation.

Abstract: This paper presents a simple power flow control method for a new contactless power transfer technology termed CPT (Capacitive Power Transfer). The rectification and power flow control are integrated using only two semiconductor devices, which are fully soft switched to achieve a wide range of output power control. Compared to traditional dynamic tuning/detuning control, the proposed method does not need any additional reactive component thus the system order is low, which helps to reduce the voltage/current overshoots and also improve the system reliability. Due to reduced component count and simple switching control, the realized system can be very compact and efficient. The theoretical analysis and design have been verified by simulation results.

Abstract: This paper presents a novel circuit failure prediction mechanism for high field reliability. On-line testing at a power-on/off time of a system detects the circuits' delay degradation that is caused by aging. Dedicated test vectors are applied using BIST architecture. Embedded ring oscillators are utilized to compensate the measured delay values for temperature or voltage shift. The concept and necessary conditions for the mechanism are introduced and some preliminary experimental results show the possible effectiveness of the approach.

Abstract: Voltage and frequency margins necessary to ensure correct processor operation under dynamic voltage, temperature, and aging variations result in performance and power overheads. Resilient circuit techniques, including embedded error-detection sequentials and tunable replica circuits, allow these margins to be reduced or eliminated, resulting in reliable, energy-efficient operation. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and design styles General Terms Performance, Design, Reliability

Abstract: The advanced electric power grid is a cyber-physical system comprised of physical components, such as transmission lines and generators, and a network of embedded systems deployed for their cyber control. The objective of this paper is to qualitatively and quantitatively analyze the reliability of this cyber-physical system. The original contribution of the approach lies in the scope of failures analyzed, which crosses the cyber-physical boundary by investigating physical manifestations of failures in cyber control. As an example of power electronics deployed to enhance and control the operation of the grid, we study Flexible AC Transmission System (FACTS) devices, which are used to alter the flow of power on specific transmission lines. Through prudent fault injection, we enumerate the failure modes of FACTS devices, as triggered by their embedded software, and evaluate their effect on the reliability of the device and the reliability of the power grid on which they are deployed. The IEEE118 bus system is used as our case study, where the physical infrastructure is supplemented with seven FACTS devices to prevent the occurrence of four previously documented potential cascading failures.

Abstract: Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.

Abstract: This paper describes the investigation of a Plasma-Induced Damage (PID) event in the metal stack of an 8-in 130-nm-high volume process line. The relevant PID stress and measurement sequence used during standard productive fast Wafer Level Reliability Monitoring, which had detected this event, is discussed, and it is shown to be very effective. Additionally, hot carrier stress was performed on MOS transistors with antenna structures connected to the gate electrode for the quantification of the effect of PID on MOS device characteristics. It is demonstrated that the complete investigation can be done on production wafers in a very short time and only on scribe line test structures, saving time and hardware cost for extra wafers.

Abstract: It was recently shown that radiation hardened by design (RHBD) annular-gate MOSFETs not only provide totaldose radiation tolerance, but can also improve the hot-carrier reliability of advanced CMOS circuits. In this paper, the hotcarrier reliability of standard two-edge and enclosed geometry transistors intended for use in space and strategic environments is demonstrated. Hot-carrier reliability measurements on standard two-edge, standard enclosed, gate under-lap enclosed, and annular transistors fabricated in the same 90 nm high performance technology indicate an improvement in hot-carrier lifetime in the enclosed geometry and multi-finger transistor designs when compared to a conventional single stripe MOSFET. Two-dimensional device simulations, along with experimental measurements, provide physical insight into the reliability response of each device type.