Abstract: With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.

Abstract: This work introduces an analytical approach to model the random threshold voltage (Vth) fluctuations in emerging high-k/metal-gate devices caused by the dependency of metal work-function (WF) on its grain orientations. It is shown that such variations can be modeled by a multi-nomial distribution where the key parameters of its probability distribution function (pdf) can be calculated in terms of the physical dimensions of the devices and properties of the materials. It is highlighted for the first time that such variations can have significant implications for the performance and reliability of minimum sized circuits such as SRAM cells.

Abstract: Strain engineering based on either a global approach using high-mobility substrates or the implementa- tion of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness Recent insights will be discussed and the influence of different strain engineering approaches illustrated

Abstract: This paper presents a procedure of supply reliability evaluation for microgrids including renewable energy sources such as wind power and photovoltaics. Microgrid system can be used as a framework to flexibly introduce the renewable energy sources. However, some renewable energy sources affect the power quality negatively. Therefore, it is important to evaluate a microgrid system adequately, and to discuss supply reliability evaluation. In this paper, the authors introduce special reliability indices for microgrids.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof capable of preventing a wafer from cracking and correcting the warpage of the wafer, preventing once-executed various reliability tests from becoming useless, and contributing to simplification of manufacturing processes and improvement of heat dissipation. SOLUTION: The backside of a semiconductor wafer 30 is ground to be thinned into a predetermined thickness, and then a metal layer 19 made of a metal having a linear expansion coefficient close to the linear expansion coefficient of the semiconductor wafer 30 is formed on the thinned surface. Next, the semiconductor wafer is sealed with a resin 20, a metal bump 21 is bonded to the top portion of a metal post 17 (barrier metal layer 18), and the wafer is divided into respective device units 10. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract: A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents poor reliability caused by metal migration and can be made small in size SOLUTION: The semiconductor device is provided with a semiconductor layer 103, and a surface insulation film 108 that is formed on the surface of the semiconductor layer 103 Contact holes 120E and 120C are formed penetrating in a part of the area of the surface insulation film 108 so that the surface of the semiconductor layer may be exposed First metal layers 109E and 109C are provided along the bottoms and the side walls of the contact holes 120E and 120C Second metal layers 111E and 111C are stacked on the first metal layers 109E and 109C COPYRIGHT: (C)2008,JPO&INPIT

Abstract: In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed technique.

Abstract: Reliability has become a practical concern in today's VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance warnings before system errors occur. This paper presents a reliability monitor design for NBTI (Negative Bias Temperature Instability). NBTI is recognized as very critical as it leads to short device lifetime. The proposed reliability monitor not only tracks the NBTI effect but also mitigates the degradation by forward biasing the PMOS. A worst case scenario static stress experiment demonstrates two orders of magnitude improvement in system lifetime using PTM 65nm technology. A ring oscillator example shows how frequency degradation can be compensated. Deployment of the proposed NBTI monitor is also discussed and two compatible strategies are provided to incorporate these monitors efficiently: the first focuses on low area overhead while the second features low power.

Abstract: A silicon carbide semiconductor power module is developed for operation at wide temperature extremes. The development of a device substrate, die-attach, interconnect system, and module DC interface is presented in this paper. Electrical and mechanical components of the package are tested and chosen for the best combination to work together as a system. This allows the package to withstand thermal cycling and demonstrate reliability through its operating temperature range of -50degC to 250degC.

Abstract: This book provides an important link between the theoretical knowledge in the field of non-linier physics and practical application problems in microelectronics. It delivers different levels of understanding of the physical phenomena that play a critical role in limitation of the semiconductor device capabilities, physical safe operating area limitation, and different scenarios of catastrophic failures in semiconductor devices. The book focuses on power semiconductor devices and self-triggering pulsed power devices for ESD protection clamps. The purpose of the book is popularization of the physical approach for reliability assurance. Another unique aspect of the book is the role of local structural defects, their mathematical description, and their impact on the reliability of the semiconductor devices. One of the major challenges the book covers is the gap in understanding of major physical regularities between the theoretical knowledge in the field of non-linier phenomena in semiconductors and the reliability and ESD protection problems in process and device development, circuit design, TCAD, and applications.

Abstract: A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number of operation cycle). Even if a level of the threshold voltage is changed to a level which differs from that of the target voltage by an increase of the accumulated number of operation cycle regardless of the programming operation (or the erasing operation) being normally performed, the reliability of the reading operation can be enhanced to prevent a malfunction of the memory cell from being generated.

Abstract: Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Parametric variation introduced by nano-scale device fabrication inaccuracy can exacerbate the PMOS transistor wear-out problem and further reduce the reliable lifetime of microprocessors. In this work, we propose microarchitecture design techniques to combat the combined effect of NBTI and process variation (PV) on the reliability of high-performance microprocessors. Experimental evaluation shows our proposed process variation aware (PV-aware) NBTI tolerant microarchitecture design techniques can considerably improve the lifetime of reliability operation while achieving an attractive trade-off with performance and power.

Abstract: PROBLEM TO BE SOLVED: To appropriately perform a reliability test when manufacturing a semiconductor device. SOLUTION: The manufacturing method of the semiconductor device includes steps (S31, S50) to determine a condition of the reliability test to be applied to semiconductor chips (2, 2a-2d) based on a substitution rate which shows percentage of normal memory cells substituted by redundant memory cells to all normal memory cells provided in the semiconductor chips (2, 2a-2d). The reliability test when manufacturing the semiconductor device is appropriately performed by determining the condition of reliability test based on the substitution rate. To put it concretely, a careful reliability test is applied to the semiconductor chips having high substitution rate, i.e. low-quality semiconductor chips, and a comparatively simple reliability test is applied to the semiconductor chips having low substitution rate, i.e. high-quality semiconductor chips. Consequently, a time required for the reliability test and a manufacturing cost for the semiconductor device are reduced. COPYRIGHT: (C)2008,JPO&INPIT

Abstract: Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase in the magnitude of PMOS threshold voltage, resulting in the degradation of circuit performance over time. NBTI is highly sensitive to operating temperature, making the amount of degradation strongly dependent on the thermal history of the chip. In order to accurately predict the amount of threshold voltage increase, the precise temperature profile must be utilized. The existing models are based on the simplified analysis which assumes that the temperature takes up to two possible fixed values over time. These models are inaccurate when predicting the impact of continuously-changing temperature that spans a large range. Our experiments show that proposed model accounting for temperature variation provides a significantly tighter bound for the simulation than that from the model that ignores the temperature variation and assumes a constant (worst-case) temperature. In our experiment, the amount of degradation predicted by the proposed dynamic temperature model is on average 46% less conservative compared to the model based on the worst-case temperature.

Abstract: This paper presents a hybrid CNT/CMOS chemical sensor system that comprises of a carbon nanotube sensor array and a CMOS interface chip The full system, including the sensor, consumes 32 muW at 183 kS/s readout rate, accomplished through an extensive use of CAD tools and a model-based architecture optimization A redundant use of CNT sensors in the frontend increases the reliability of the system

Abstract: Electromigration is a well-known root-cause for long-term reliability problems. This paper demonstrates that the resistance to electromigration is significantly increased when solder-based intermetallic bonding is used as an alternative to standard solder flip-chip interconnections. Two different intermetallic joint-types are investigated: Cu-Sn and Co-Sn. After 1000h, no failures or degradation mechanisms are observed for testing conditions (150°C and 0.63mA/?m2) which are 10 times harsher in terms of current density compared to electromigration triggering density values for standard solder flip-chip applications (0.05mA/?m2).

Abstract: Eighteen sodium-cooled fast reactors (SFRs), a number that includes reactors in operation or shut down, have provided 388 reactor-years of operating experience to date. This paper summarizes the important incidents related to fast reactor sodium components and systems. The solutions incorporated, based on experience, analysis, experimental tests, and research and development for past and current SFRs, are described. The paper also describes lessons learned for future SFRs.

Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111 a and 115 a , a third insulating film 113 having the smallest bandgap 113 a , and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115 , respectively, and having intermediate bandgaps 112 a and 114 a.

Abstract: Increasing levels of integration in field programmable gate arrays, have resulted in high on-chip power densities, and temperatures. The heterogeneity of components and scaled feature sizes in platform FPGAs have made them vulnerable to various temperature dependent failure mechanisms. Hence, we need to introduce temperature awareness in tackling such failures that affect the lifetime reliability of FPGAs. In this paper, we present a dynamic thermal-aware reliability management (DTRM) framework to analyze the impact of temperature variations on the longterm/lifetime reliability of Platform FPGAs. We first study the temperature variations, both across and with-in designs, due to the use of various hard-blocks within a 65 nm platform FPGA. In the presence of such variations, we demonstrate the vulnerability of Platform FPGAs to two different hard-failures, namely, Electromigration, and time dependent dielectric breakdown (TDDB). We also analyze the performance degradation caused by Negative Bias Temperature Instability (NBTI) in the presence of thermal-variations. We validate the temperature variations estimated by the DTRM framework using a ring oscillator based real-time temperature measurement technique.

Abstract: In this paper, we focus on critical issues directly related to the viability of carbon nanotube-based nanoelectromechanical switches, to perform their intended functionality as logic and memory elements, through assessment of typical performance parameters with reference to complementary metal-oxide-semiconductor devices. A detailed analysis of performance metrics regarding threshold voltage control, static and dynamic power dissipation, speed, and integration density is presented. Apart from packaging and reliability issues, these switches seem to be competitive in low power, particularly low-standby power, logic and memory applications.

Abstract: A response control method for the lower voltage traversing of a wind generating set is characterized in that changing situation of the voltage us of a power network is detected at any time; the power the voltage us of the power network is compared with a reference value of the voltage us of the power network, and a wattless current iqref as well as an effort current idref are obtained by an obtained difference value Delta u through a PI adjustor; the wattless current iqref is taken as the reference value for the inner loop control of the circuit to cooperate with the control strategies of the outer loop of the voltage and the inner loop of the circuit to control a network side inverter and restrain the depreciation of the voltage of the power network as well as the effect loss of the compensating chain of the effect circuit idref . Under the situation that the voltage of the power network declines instantly, the invention can flexibly feed corresponding reactive powers according to requirements, adjust the effect power correspondingly as well, lead the wind generating set to reach a transmission reliability standard similar to a fire generating set, and has the capacity of self adjustment.

Abstract: Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxide thickness varies from die-to-die and within-die and as the precision of process control worsens an alternative reliability analysis approach is needed. In this work, we propose a statistical framework for chip level gate oxide reliability analysis while considering both die-to-die and within-die components of thickness variation. The thickness of each device is modeled as a distinct random variable and thus the full chip reliability estimation problem is defined on a huge sample space of several million devices. We observe that the full chip oxide reliability is independent of the relative location of the individual devices. This enables us to transform the problem such that the resulting representation can be expressed in terms of only two distinct random variables. Using this transformation we present a computationally efficient and accurate approach for estimating the full chip reliability while considering spatial correlations of gate-oxide thickness. We show that, compared to Monte Carlo simulation, the proposed method incurs an error of only 1~6% while improving the runtime by around three orders.

Abstract: This paper presents a methodology for integrating reliability considerations into the performance analysis carried out during the design of fault-tolerant power converters. The methodology relies on using a state-space representation of the power converter, based on averaging, similar to the ones used when analyzing linear time-invariant systems, and assumes an unknown-but-bounded uncertainty model for the converter uncontrolled inputs, such as load or variations in input voltage. The converter must be designed such that, for any uncontrolled input, the state variables remain within a region of the state space defined by performance requirements, e.g., output voltage tolerance or switch ratings. In the presence of component faults, and depending on the uncontrolled inputs, the converter may or may not meet performance requirements. Given the uncertain nature of these uncontrolled inputs, and for each particular fault, we introduce an analytical method to compute the probability that the performance requirements are met, which will define the reliability of the converter for each particular fault. By including these probabilities in a Markov reliability model, it is possible to obtain the overall converter reliability. The application of the methodology is illustrated with a case study of a fault-tolerant interleaved buck converter.

Abstract: Silicon carbide possesses excellent material properties for high temperature, high frequency and high power applications. Among all the device structures, MOSFET has advantages such as low gate leakage current, easier device control etc., and therefore highly desirable. However, it has long been a common believe that the gate oxide breakdown reliability is a show-stopper, particularly at high temperature where SiC devices are expected to excel. In this paper, we report that the thermally grown gate oxide on 4H-SiC is intrinsically reliable even at temperature as high as 375degC. We further show that even with the current SiC processing technology, devices with 10 cm2 active area can still achieve 100-year lifetime @ E < 2.9 MV/cm and 375degC.

Abstract: Detecting insulation flaws in HVDC apparatus, where partial discharge (PD) may occur can help preventing failures, even if the degradation rate under PD is much slower than in AC conditions. In order to improve reliability of HVDC systems and, in particular of HVDC transmission lines, it would be important to distinguish defects of different harmfulness. However, under DC voltage the concept of phase-resolved PD pattern loses meaning and conventional techniques for PD source identification are no longer applicable. Techniques based on the statistical correlation between subsequent PD events have been proposed to identify PD sources under DC voltage. In this paper, the search for novel features able to characterize different phenomena (that can be described in broad terms as internal, surface and corona PD) is carried out. In particular, besides additional markers that have not been presented yet in literature, it is proposed to exploit the polarity- and voltage-dependent characteristics of different PD phenomena.

Abstract: This report summarizes efforts to reconfigure loads during outages to allow individual customers the opportunity to enhance the reliability of their electric service through the management of their loads, photovoltaics, and energy storage devices.