Abstract: Application of individual distributed generators can cause as many problems as it may solve. A better way to realize the emerging potential of distributed generation is to take a system approach which views generation and associated loads as a subsystem or a "microgrid". The sources can operate in parallel to the grid or can operate in island, providing UPS services. The system will disconnect from the utility during large events (i.e. faults, voltage collapses), but may also intentionally disconnect when the quality of power from the grid falls below certain standards. Utilization of waste heat from the sources will increase total efficiency, making the project more financially attractive. Field verification of the Consortium for Electric Reliability Technology Solutions (CERTS) microgrid control concepts are included.

Abstract: In this paper, a procedure is presented for the life estimation of high-voltage cables subjected to electrothermal stress due to applied voltage and load cycles. Thermal transients that affect cable insulation as a consequence of cyclic current variations are modeled by means of the well-known CIGRE two-loop thermal network analog. The effect of the relevant cyclically varying electrothermal stress is accounted for via the cumulative damage law of Miner. The life fractions lost during each step of the load cycle are evaluated by resorting to a proper combined electrothermal life model holding for cable insulation. The model is considered within its due probabilistic framework for associating life with residual reliability and failure probability. The procedure is applied to high-voltage ac EPR- and XLPE-insulated cables, subjected to stepwise-constant daily load cycles. The application shows that life is very sensitive to load cycles, as well as to thermal transients and to the synergism between electrical and thermal stress. Thus, none of these factors should be neglected for an accurate estimate of life expectancy of high-voltage cables in real service conditions.

Abstract: The impact reliability of solder joints in electronic packages is critical to the lifetime of electronic products, especially those portable devices using area array packages such as ball-grid array (BGA) and chip-scale packages (CSP). Currently, SnAgCu (SAC) solders are most widely used for lead-free applications. However, BGA and CSP solder joints using SAC alloys are fragile and prone to premature interfacial failure, especially under shock loading. To further enhance impact reliability, a family of SAC alloys doped with a small amount of additives such as Mn, Ce, Ti, Bi, and Y was developed. The effects of doping elements on drop test performance, creep resistance, and microstructure of the solder joints were investigated, and the solder joints made with the modified alloys exhibited significantly higher impact reliability.

Abstract: Today's embedded systems integrate multiple IP cores for processing, communication, and sensing on a single die as systems-on-chip (SoCs). Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature have made reliability assessment a much more significant issue. Although reliability of devices and interconnect has been broadly studied, in this work, we study a tradeoff between reliability and power consumption for component-based SoC designs. We specifically focus on hard error rates as they cause a device to permanently stop operating. We also present a joint reliability and power management optimization problem whose solution is an optimal management policy. When careful joint policy optimization is performed, we obtain a significant improvement in energy consumption (40%) in tandem with meeting a reliability constraint for all SoC operating temperatures

Abstract: Polymer electrolyte fuel cells (FCs) are often considered as the most promising power-generation sources for next- generation electrical or hybrid electrical vehicles. However, areas needing further development are the improvements of the efficiency, durability, and reliability of the whole powertrain. Moreover, freeze start of the FC system is also a major issue. To reach these aims, diagnosis solutions of FC stacks and systems can speed up the development cycle of this new technology. The aim of this paper is, thus, to propose some guidelines within the framework of embedded FC system durability diagnosis.

Abstract: Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years

Abstract: This paper describes the fundamental insulation characteristics of environmentally friendly gases; dry air, N2 and N2 O2 mixed gas. Conventional gas insulated switchgear (GIS) generally uses SF6 as against over 72.5 kV class. We have proposed GIS with a vacuum circuit breaker against from 72.5 kV class to 170 kV class as SF6-free GIS. Because the insulation gas of this type of SF6 -free GIS has the hardly unnecessary current interception performance, the optimal insulation gas can be selected based on fundamental insulation performance. From the standpoints of insulation performance and economical efficiency, we selected compressed dry air as the optimal insulation gas for this type of SF6-free GIS. However, the dielectric strength of dry air is approximately one-third that of SF6 gas. Therefore, to achieve roughly the same size as conventional GIS, some strategies must be employed to enhance insulation performance. This paper investigates the influence of gas pressure and a gas/solid hybrid insulation structure. The insulation performance of the gas/solid hybrid insulation structure using an insulation coating was found to be better than that of a barrier. Moreover, the dielectric strength of particles adhering to a spacer under the compressed dry air was about 1.5 times higher than that under N2. Thus, the high insulation reliability of the gas/solid hybrid structure was high against particles was confirmed. In view of these investigative findings, this type of SF6-free 72.5 kV GIS which was designed and manufactured, was confirmed to comply with the IEC standard.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of improving the reliability of data.SOLUTION: A semiconductor storage device of an embodiment includes: a plurality of memory cells capable of holding data; a plurality of word lines connected to the plurality of memory cells; and a control unit. The control unit performs: a first step for applying a first write voltage to a word line which is selected out of the plurality of word lines and applying a first verify voltage and a second verify voltage higher than the first verify voltage; and a second step for applying a third verify voltage lower than the first verify voltage and a fourth verify voltage lower than the second verify voltage and higher than the third verify voltage to the word line which is selected out of the plurality of word lines after the first step.

Abstract: There is a trend toward increasing the performance of power electronics converters used in photovoltaic systems. However, parameters such as reliability, efficiency, and complexity might be in conflict. In this paper, the design of a simple DC/DC interleaved boost converter is assessed. It takes advantage of state-of-the-art power devices that have fast switching times. It is shown that requirements of low complexity, high reliability, and high efficiency can be satisfied, without resorting to switching aids, provided that the devices are selected with reliability in mind. A 1 kW prototype attained a peak efficiency as high as 98%, and a predicted mean time between failures of 100,000 hours at 80 C.

Abstract: A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method.

Abstract: The knowledge of the condition of electrical equipment of power systems is a fundamental part for the reliability of energy systems. For the evaluation of the insulation condition of high voltage power equipment the partial discharge detection is one standard instrument. As diagnostic tool the partial discharge measurement is used in many applications, for testing and comparing different types of insulating materials and also to check complete devices or systems. Improvements, new developments as well as lower costs of sensors, processing and analysing units are some reasons for the increasing of PD diagnostic systems. This paper presents an overview about technologies for the optical partial discharge detection. Based on the emitted light produced by ionization, excitation and recombination processes during the discharge different parameters must be considered and diverse detection techniques are discussed. Additional some fundamental investigations of the discharge properties and their temporal behaviour in different insulation mediums were examined with a developed optical PD-detection system.

Abstract: A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.

Abstract: Introduction - Reliability Issues in MEMS Part I: Mechanical Reliability of MEMS Materials Mechanical Properties of MEMS Materials Micro/Nano-Indenters Bulge Methods Bending Test using Probe Tools Uni-axial Tensile Test with Specialized Chucking Methods On-chip Microstructures Part II: Reliability of MEMS Devices Pressure Sensors Inertial Sensors RF MEMS Optical MEMS

Abstract: This invention aims at improvement in reliability of a semiconductor device. In this invention, a semiconductor wafer is irradiated with laser light so as to have a fractured layer formed in the interior of the semiconductor wafer, the semiconductor wafer is mounted on a dicing tape via paste (adhesive layer), then the paste of the dicing tape is hardened by UV irradiation or cooling, and subsequently the semiconductor wafer is bent (breaking). By this process, shifting and movement of semiconductor chips can be prevented because the paste has been hardened at the time of the bending. As a result, the semiconductor chip can be prevented from interfering with adjacent chips and can also be inhibited from generating chipping; therefore, the reliability of a semiconductor device can be improved.

Abstract: Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology alternatives. Reliability analysis of logic circuits is NP-hard because of the exponential number of inputs, combinations and correlations in gate failures, and their propagation and interaction at multiple primary outputs. By coupling probability theory with concepts from testing and logic synthesis, this paper presents accurate and scalable algorithms for reliability analysis of logic circuits. Simulation results for several benchmark circuits demonstrate the accuracy, performance, and potential applications of the proposed analysis technique.

Abstract: Kufluoglu, Haldun Ph.D., Purdue University, December, 2007. MOSFET Degradation due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) and Its Implications for Reliability-aware VLSI Design . Major Professor: Muhammad A. Alam. The scaling trends in CMOS technology and operating conditions give rise to serious degradation mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) in MOSFETs, threatening the circuit and product lifetimes. The aging phenomena, on top of process variations, translate into complexity and reduced design margin for circuits. International Technology Roadmap for Semiconductors mentions reliability as one of the ”Design Technology Challenges” and calls attention to ”Design for Reliability.” In order to increase the overall design efficiency, it is important to (i) understand MOSFET-level degradation, (ii) develop physically robust compact models compatible with circuit simulators, and (iii) implementing tools that incorporate NBTI and HCI reliability into VLSI design process at an early stage. In this work, NBTI and HCI degradation and their implications on MOSFET and circuit reliability are studied. Transistor-level NBTI degradation is explored and experimentally calibrated voltage, temperature, and time dependences are obtained. Recovery characteristics, degradation under AC and random activity relations are derived. Implications for aggressively-scaled and non-planar MOSFET geometries are discussed. With comprehensive experimental and theoretical tools, HCI degradation is investigated, particularly for short channel MOSFETs with lower operating conditions. HCI issues that are unclear in the literature are resolved. The interface trap generation under HCI is linked to NBTI theory, thus degradation of circuits experiencing both mechanisms can be assessed efficiently. Finally, compact

Abstract: This paper presents the fabrication and experimental results of capacitive MEM switches with a carbon nanotubes (CNT) based dielectric for the first time to our knowledge. Double wall nanotubes (DWNT) have been incorporated in the switch silicon nitride dielectric to modify its properties regarding the charging effect. The impact of the CNT density on the MEMS reliability has been demonstrated: a switch lifetime enhancement greater than two orders of magnitude has been achieved.

Abstract: This paper discusses the reliability of power electronics modules. The approach taken combines numerical modeling techniques with experimentation and accelerated testing to identify failure modes and mechanisms for the power module structure and most importantly the root cause of a potential failure. The paper details results for two types of failure (i) wire bond fatigue and (ii) substrate delamination. Finite element method modeling techniques have been used to predict the stress distribution within the module structures. A response surface optimisation approach has been employed to enable the optimal design and parameter sensitivity to be determined. The response surface is used by a Monte Carlo method to determine the effects of uncertainty in the design.