TL;DR: In this paper, the ion sources, systems and methods can enhance the ability to make tips having desired physical attributes (e.g., the number of atoms on the apex of the tip).
Abstract: Ion sources, systems and methods are disclosed. In some embodiments, the ion sources, systems and methods can exhibit relatively little undesired vibration and/or can sufficiently dampen undesired vibration. This can enhance performance (e.g., increase reliability, stability and the like). In certain embodiments, the ion sources, systems and methods can enhance the ability to make tips having desired physical attributes (e.g., the number of atoms on the apex of the tip). This can enhance performance (e.g., increase reliability, stability and the like).
TL;DR: Interconnect RC time-delay worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects, and the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts.
Abstract: Scaling, for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits.This will require that designers will have to be very careful with: high current densities,voltage overshoots, localized hot spots on the chip, high duty-cycle applications, and high thermal-resistance packaging.In addition to the reliability issues, interconnect RC time-delay will worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects.Also, the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts.
TL;DR: The intrinsic failure mechanisms and reliability models of state-of-the-art MOSFETs are reviewed and a new approach for accurately predicting circuit reliability and failure rate from the system point of view is proposed.
TL;DR: In this article, the authors present the application of compact insulated gate bipolar transistor and p-i-n diode models, including features such as local lifetime control and field-stop technology, to the full electrothermal system simulation of a hybrid electric vehicle converter using a lookup table of device losses.
Abstract: This paper presents the application of compact insulated gate bipolar transistor and p-i-n diode models, including features such as local lifetime control and field-stop technology, to the full electrothermal system simulation of a hybrid electric vehicle converter using a lookup table of device losses. The vehicle converter is simulated with an urban driving cycle (the federal urban driving schedule), which is used to generate transient device temperature profiles. A methodology is also described to explore the converter reliability using the temperature profile, with rainflow cycle counting techniques from material fatigue analysis. The effects of ambient temperature, driving style, and converter design on converter reliability are also investigated.
TL;DR: In this paper, the authors compared several rectifier-inverter and matrix converter topologies suitable for aerospace applications, and their reliability is predicted using MIL-HDBK-217F guidelines.
Abstract: Several rectifier-inverter and matrix converter topologies suitable for aerospace applications are compared, and their reliability is predicted. The military handbook MIL-HDBK-217F guidelines have been used to predictreliability. The matrix converter has several attractive features for aerospace applications such as potential size and weight savings. Although the matrix converter has a higher number of semiconductor switches, they are subjected to a lower voltage stress, which decreases their failure rate. This results in the reliability indicators of the different converter topologies being very similar
TL;DR: In this article, an investigation into the reliabilities of generators and converters in such configurations and is based on failure data collected in Germany and Denmark is presented, which draws conclusions about which configurations have the higher reliability and identifies the subassemblies of the turbines which require attention for the future design of high reliability wind turbines.
Abstract: Electrical Machine/Converter combinations are used in a variety of applications, from powers of Watts to MegaWatts. Some applications, such as propulsion and generation, have high reliability & availability requirements. Modem large wind turbines incorporate variable pitch blades and a variable speed Generator, which feeds the Grid through a Converter and have a need for high reliability & availability. There are a number of configurations of generator and converter intended to provide optimum performance for present and future wind power. This paper describes an investigation into the reliabilities of Generators and Converters in such configurations and is based on failure data collected in Germany and Denmark. The paper draws conclusions about which configurations have the higher reliability and identifies the subassemblies of the turbines which require attention for the future design of high reliability wind turbines. Recommendations are made about how designers and operators of wind turbines can increase their reliability by the choice of Concept and the operating regime
TL;DR: This book reviews the significance of the junction temperature as a reliability measure under nominal and burn-in conditions and provides an insight into the concept of thermal runaway and how it may best be avoided.
Abstract: In Thermal and Power Management of Integrated Circuits, power and thermal management issues in integrated circuits during normal operating conditions and stress operating conditions are addressed. Thermal management in VLSI circuits is becoming an integral part of the design, test, and manufacturing. Proper thermal management is the key to achieve high performance, quality and reliability. Performance and reliability of integrated circuits are strong functions of the junction temperature. A small increase in junction temperature may result in significant reduction in the device lifetime. This book reviews the significance of the junction temperature as a reliability measure under nominal and burn-in conditions. The latest research in the area of electro-thermal modeling of integrated circuits will also be presented. Recent models and associated CAD tools are covered and various techniques at the circuit and system levels are reviewed. Subsequently, the authors provide an insight into the concept of thermal runaway and how it may best be avoided. A section on low temperature operation of integrated circuits concludes the book.
TL;DR: In this article, the authors examine how MEMS reliability is handled in commercial MEMS devices used in safety critical applications on earth and contrast the operating conditions on earth with those encountered during launch and in orbit.
Abstract: With their extremely low mass and volume, low power consumption and tight integration with electronics, MEMS sensors and actuators are extremely appealing for reducing the size and mass of spacecraft without sacrificing functionality. In view of the harsh and remote environment of space, reliability and qualification is the crucial issues that are holding back MEMS from playing a larger role in space applications. We examine how MEMS reliability is handled in commercial MEMS devices used in safety critical applications on earth and contrast the operating conditions on earth with those encountered during launch and in orbit. We explain the impact that vibration, mechanical and thermal shock, and radiation can have on MEMS devices fabricated using the most widespread silicon technologies. Accelerated tests adapted to space qualification are presented as a means to determine the major failure modes. Hermetic packaging is crucial to ensuring long-term reliability.
TL;DR: In this article, a novel embedded one-time programmable (OTP) nonvolatile memory (NVM) using only standard Foundry CMOS logic technology is described, and reliability data is presented for 1Mb memory modules fabricated in 0.18mu technology.
Abstract: A novel embedded one-time programmable (OTP) nonvolatile memory (NVM), using only standard Foundry CMOS logic technology, is described. IP modules with densities from 1Kb to 1Mb were constructed and tested. Reliability data is presented for 1Mb memory modules fabricated in 0.18mu technology
TL;DR: Details of the operation, performance and reliability of Freescale's commercial 4Mbit MRAM device will be presented and operation and reliability results demonstrating the extension of toggle MRAM to meet industrial and automotive requirements are presented.
Abstract: This paper provide an overview of the recent progress and the nature outlook of MRAM technology. Details of the operation, performance and reliability of Freescale's commercial 4Mbit MRAM device will be presented. Operation and reliability results demonstrating the extension of toggle MRAM to meet industrial and automotive requirements are presented, and new research results on higher-performance materials and advanced scaling approaches are discussed
TL;DR: A qualification methodology is demonstrated to define an optimized reliable electrical fuse programming window by combining fuse resistance measurements, physical analysis, and functional sensing data that addresses the impact on electrical fuse reliability caused by process variation and device degradation.
Abstract: The reliability of CoSi2/p-poly Si electrical fuse (eFUSE) programmed by electromigration for 90nm technology will be presented. Both programmed and unprogrammed fuse elements were shown to be stable through extensive reliability evaluations. A qualification methodology is demonstrated to define an optimized reliable electrical fuse programming window by combining fuse resistance measurements, physical analysis, and functional sensing data. This methodology addresses the impact on electrical fuse reliability caused by process variation and device degradation (e.g., NBTI) in the sensing circuit and allows an adequate margin to ensure electrical fuse reliability over the chip lifetime.
TL;DR: In this paper, an accurate physics-based compact model of the devices is proposed: it includes all important electrothermal effects relevant to the description of the observed failure mechanisms, including mutual heating effects between neighboring devices.
Abstract: This paper analyzes the operation of PowerMOSFETs in the 42-V-PowerNet and shows that very stressful conditions are encountered, which can lead to severe reliability problems. To enable thorough investigations by circuit simulations an accurate physics-based compact model of the devices is proposed: it includes all important electrothermal effects relevant to the description of the observed failure mechanisms. By means of an advanced thermal-modeling approach, multichip assemblies can be accurately described, including mutual heating effects between neighboring devices. Some properly chosen examples demonstrate the validity of the model and its usefulness for reliability investigations
TL;DR: The results suggest that wire-bonding optimization by thermo-electric simulation can contribute not only to realizing more compact power modules but also to improving the module reliability.
TL;DR: In this article, a method for identifying the type and location for protection devices and switches on the prerouted distribution system using value-based optimization is proposed, which is based on the contingency analysis of various components, e.g., the faults of line sections, switches, and the restoration through switching actions such as upstream restoration and downstream restoration.
Abstract: The protective devices and switches play an important role in the reliability of electrical distribution systems by minimizing the impact of interruption. In this paper, a method for identifying the type and location for protection devices and switches on the prerouted distribution system using value-based optimization is proposed. The proposed method is based on the contingency analysis of various components, e.g., the faults of line sections, switches, protective devices, and the restoration through switching actions such as upstream restoration and downstream restoration. The formulation of the optimization problem in this paper is appropriate for linear integer programming, where each nonlinear term can be translated by only two additional linear constraints. The detailed design of the protection devices and the switches are determined by minimizing the total cost of reliability that comprises apparatus investment, maintenance, and interruption cost. The efficiency and validity of the proposed method are demonstrated in case studies.
TL;DR: This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation, and extends the analysis to parallel programming by incorporating Amdahl's law in the authors' equations.
Abstract: Challenges in multicore processor design include meeting demands for performance, power, and reliability. The progression towards deep submicron process technologies entails increasing challenges of process variability resulting in timing instabilities and leakage power variation. This work introduces an analytical approach for ensuring timing reliability while meeting the appropriate performance and power demands in spite of process variation. We validate our analytical model using Turandot to simulate an 8-core PowerPCtrade processor. We first examine a simplified case of our model on a platform running independent multiprogrammed workloads consisting of all 26 of the SPEC 2000 benchmarks. Our simple model accurately predicts the cutoff point with a mean error less than 0.5 W. Next, we extend our analysis to parallel programming by incorporating Amdahl's law in our equations. We use this relation to establish limit properties of power-performance for scaling parallel applications, and validate our findings using 8 applications from the SPLASH-2 benchmark suite
TL;DR: A robust design solution is suggested to reduce the mechanical stress and improve the assembly yield and reliability and a degradation model is proposed with the support of detail failure analysis.
Abstract: The paper investigated the thin film stress effect on the wire-bond assembly yield and reliability. ESD layouts that utilize the bond pad area increase the thermo-mechanical stress of the thin-films in the pad area and affect the assembly. Experimental data on products with different metal layout designs are compared to characterize the assembly yield and reliability performance. A computer finite element mechanical stress analysis is also conducted to quantify the interaction of pad design with the assembly. Experimental data and simulation showed a good correlation between the metal layout and the assembly yield and reliability. A degradation model is proposed with the support of detail failure analysis. A robust design solution will be suggested to reduce the mechanical stress and improve the assembly yield and reliability.
TL;DR: Based on field return and test data, the major failure mechanisms and failure modes of cooling fan system are presented in this article, and failure criteria and the reliability metrics for cooling fan systems are discussed.
Abstract: Based on field return and test data, the major failure mechanisms and failure modes of cooling fan system are presented in this paper. Then, the failure criteria and the reliability metrics for cooling fan systems are discussed. By critically comparing the accelerated life testing methods from various vendors, a practical accelerated life testing methodology is presented. The acceleration testing models and acceleration factor are also discussed. In the last section, a comprehensive reliability qualification procedure is proposed
TL;DR: In this paper, a detailed examination of particle temperature distributions is presented, and a significant structure in the statistical distribution has been observed, which can be interpreted as melting state indicator for YSZ.
Abstract: Plasma sprayed coatings of Yttria Stabilized Zirconia (YSZ) have been studied extensively through the years to understand variations in coating properties as well as to achieve control on microstructure of the coatings. The requirement for microstructural control and reliability have become all the more important as coatings have now become part of an integrated “prime reliant” design strategy aimed at increasing turbine inlet temperature and associated efficiencies. One of the important thrusts in monitoring and controlling the process has been the application of process sensors that measure spray stream characteristics, notably particle temperature and velocity. Although single particle-based measurements have been available for some time, in general control strategies based on particle state rely on average values of temperature and velocity. In this study, a detailed examination of particle temperature distributions is presented. When systematically examined over a wide range of operating conditions of the resulting range of particle temperatures, a significant structure in the statistical distribution has been observed. A close inspection of the data indicates that this distribution can be interpreted as melting state indicator for YSZ. A characteristic peak at the melting point of ZrO2 (error in absolute T-measurement is ≈ ±10%) can be used as an indicator for re-solidified particles. In the past, control strategies based on process diagnostic sensors have been based on average particle temperatures and velocities. Although the average values seem to be promising as control parameters, it has been shown through our results that different melting states could be demonstrated for the same average T and V settings. The melting state in turn has an important bearing on the coating structure and properties. It therefore implies that a process control strategy (to maintain coating quality) based on in flight particle sensors will have to take these findings into account. As an example, one strategy of process control would not only define the process in terms of the average particle temperature and velocity but also include the effect that parameter changes have on distributions.
TL;DR: High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce, and this article shows that the use of HVST can dramatically reduce the amount of required burn- in.
Abstract: To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in.
TL;DR: The concept of threshold voltage in undoped-body MOSFETs is examined and various existing criteria are analyzed and compared in an effort to clarify the ambiguity of the meaning of threshold and understand its dependence on technological parameters in these devices.
TL;DR: In this article, a new structure of power integrated converter is presented, which answers the requirement on weight, volume and cost reduction while improving the reliability, and presents the technology approach, the electrical characteristics of these integrated structure and some reliability aspects.
Abstract: A new structure of power integrated converter is presented. These converters have been developed with standard IGBT chips and address the application of train traction drives. This new approach answers the requirement on weight, volume and cost reduction while improving the reliability. This paper presents the technology approach, the electrical characteristics of these integrated structure and some reliability aspects.
TL;DR: In this article, different ways to simultaneously control event sensing reliability and device utilization in a beacon-enabled IEEE 802.15.4 sensor cluster are investigated, where probabilistic control of the duration of active and inactive (i.e., service and sleep) periods are derived as functions of the required event-sensing reliability, device utilization, medium access control and physical layer parameters.
Abstract: Different ways to simultaneously control event sensing reliability and device utilization in a beacon-enabled IEEE 802.15.4 sensor cluster are investigated. Activity management is achieved through probabilistic control of the duration of active and inactive (i.e., service and sleep) periods. The probabilistic control parameters are derived as functions of the required event sensing reliability, device utilization, medium access control and physical layer parameters, and network size
TL;DR: For the future it is necessary that test conditions must follow the field requirements to guarantee optimum reliability results, and the importance of design for reliability based on results of simulations for a leadless package is highlighted.
TL;DR: A fast Fourier analysis-based approach is presented for obtaining temperature profiles for power semiconductors and can be used for predicting lifetime and reliability level of power circuits easily.
Abstract: Accurate prediction of temperature variation of power semiconductor devices in power electronic circuits is important to obtain optimum designs and estimate reliability levels. Temperature estimation of power electronic devices has generally been performed using transient thermal equivalent circuits. In the presence of varying load cycles, it has been typical to resort to a time-domain electrical simulation tool such as P-Spice or SABER to obtain a time series of the temperature profiles. However, for complex and periodic load cycles, time-series simulation is time consuming. In this paper, a fast Fourier analysis-based approach is presented for obtaining temperature profiles for power semiconductors. The model can be implemented readily into a spreadsheet or simple mathematical algebraic calculation software. The technique can be used for predicting lifetime and reliability level of power circuits easily. Details of the analytical approach and illustrative examples are presented in this paper.
TL;DR: In this paper, the authors investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions).
Abstract: We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.
TL;DR: In this article, the impact of substrate bias V/sub SUB/ on hot-carrier reliability is presented, and the effects of future scaling are discussed using a quasi-two-dimensional model.
Abstract: Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias V/sub SUB/ on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias V/sub SUB/ can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology.
TL;DR: In this article, the authors show that MOS and bipolar device radiation response can change significantly with aging time after device fabrication and/or packaging, due to the motion and reactions of water and other hydrogen-related species.
Abstract: Recent work is reviewed that shows that MOS and bipolar device radiation response can change significantly with aging time after device fabrication and/or packaging. Effects include changes in radiation response due to burn-in, pre-irradiation elevated temperature stress, and/or long-term storage. These changes are attributed experimentally and theoretically to the motion and reactions of water and other hydrogen-related species. Similar hydrogen-related reactions can also affect the long-term reliability of MOS devices and integrated circuits, as illustrated in detail here for negative-bias temperature instability
TL;DR: In this paper, the gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies, and a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.
Abstract: The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.