Abstract: Binary mode memory cells each storing data of a single bit per cell and multilevel mode memory cells each storing data of multi bits per cell are allocated with different address regions in a fixed manner and are formed in different regions. According to the fixed address allocation, the binary mode memory cells and the multilevel mode memory cells can be optimized individually and separately. In this way, the reliability of a nonvolatile semiconductor memory device is improved and the area occupied by the memory arrays is reduced.

Abstract: Objectives: Pre-season or pre-participation screening is commonly used to identify intrinsic risk factors for sports injury. Tests chosen are generally based on clinical experience due to the paucity of quality injury risk factor studies for sport and, often, the reliability of these clinical tests has not been established. The purpose of this study was to establish the reliability of eight, musculoskeletal screening tests, commonly used in the screening protocols of elite-level Australian football clubs. Methods: Fifteen participants (n=9 female, n=6 male) were tested by two raters on two occasions, 1 week apart to establish the inter-rater and test–retest reliability of the chosen measurement tools. The tests of interest were Sit and Reach, Active Knee Extension, Passive Straight Leg Raise, slump, active hip internal rotation range of movement (ROM), active hip external rotation ROM, lumbar spine extension ROM and the Modified Thomas Test. Results: All tests demonstrated very good to excellent (Intraclass correlation coefficient, ICC 0.88–0.97) inter-rater reliability. Test–retest reliability was also shown to be good for these tests (ICC 0.63–0.99). Conclusion: The findings suggest that these simple, clinical measures of flexibility and ROM are reliable and support their use as pre-participation screening tools for sports participants.

Abstract: Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. This model is verified with numerical solutions. With this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. In fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. Even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. Therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. This model is similarly useful for temperature-aware dynamic runtime management.

Abstract: The invention provides an optical device that enables a mutual electrical connection between the stacked semiconductor substrates to be realized with ease and high reliability and to provide for miniaturization. The optical device has a first semiconductor substrate having an optical part and a first pad, a second semiconductor substrate having an integrated circuit and a second pad which is stacked under the first semiconductor substrate, a through-hole continuously extending through the first and the second semiconductor substrate, and a conductive part so formed as to include the inside of the through-hole.

Abstract: A current control device for driving LED devices uses a switched-mode current control loop inside of an output intensity low-frequency pulse width modulation (PWM) control loop. This allows separate control of current level (for accurate light wavelength output) and light intensity. The current control device requires only one switch to regulate current level, and no other switches for the intensity control. This allows lower parts count for greater reliability and lower system cost.

Abstract: A temperature sensing circuit has numerous trip points in conformity with a temperature change without adding decrease resistance branches, so as to obtain a fine control based on the temperature change. Accordingly, when employed in a semiconductor memory device, the temperature sensing circuit substantially reduces the consumption of refresh electrical power in a stand-by state without decreasing the reliability of the semiconductor memory device.

Abstract: An information storage apparatus having internal structure and arrangement of fans in consideration of cooling effect, thereby the capacity of the entire apparatus can be smaller than that of conventional apparatus, and an optimum air channel can be formed so as to prevent damage to reliability of performance, life and the like of components at high temperatures. For a module with reliability of life or the like to be ensured or a module including a part influenced by performance such as information processing speed, provided is an arrangement where outside air is directly forwarded to the module. Further, a module which does not produce much amount of heat and does not require cooling is provided in a comparatively front stage of the channel, a module including heat-producing components and a cooling fan is provided in a comparatively rear stage of the channel.

Abstract: Application of IGBTs (insulated gate bipolar transistors) to high voltage power electronics systems is today becoming an attractive solution because of low cost and low complexity. Semiconductor manufacturers are making efforts to design chips with higher blocking voltages, but for reliability and cost purposes, an easier solution today would be to use standard IGBTs. This paper describes the behaviour of 3.3 kV, 100 A chips connected in series and driven with an active gate control circuit which balances the voltage during both static and dynamic phase. The first part of the article presents the theoretical description of the principle and some design recommendations. The second part contains experimental results. These tests demonstrated that it is possible to safely turn off two times the nominal current under 4 kV DC link voltage. Finally, short-circuit turn-off has been also successfully tested, showing a good balancing of the overvoltages, even under such emergency conditions.

Abstract: PROBLEM TO BE SOLVED: To improve property of lack of reliability in power supply resulting from disorder of the whole feed-back system because of a decrease in voltage reliability while oscillation in current and voltage is caused by a reactor and a capacitor integrated in a switching power supply through resonance, and a delay of phase of transfer function becomes not less than 180°. SOLUTION: Deterioration of property is caused by circuit operation condition for resonating a reactor and a capacitor, and these operations are restricted. A first means restricts a current caused to flow in the reactor, and prevents the resonance current. A second means prevents current of low frequency in the capacitor, and prevents a voltage variation of the capacitor voltage. In this way, the output voltage variation caused by resonance can be prevented and voltage accuracy is improved. At the same time, phase delay of transfer function becomes 90° or smaller, generation of disorder can be prevented, and reliability as power supply can be improved. COPYRIGHT: (C)2008,JPO&INPIT

Abstract: With the growing power dissipation in modem high performance VLSI designs, nonuniform temperature distribution and limited heat-conduction capability have caused thermal induced performance and reliability degradation. However the problem modeled by finite difference method for interconnect reliability analysis has huge size if we require the resolution with wire width. In addition, the generated lumped circuit has significant number of input sources, and the bottleneck of traditional model reduction methods is the big number of input ports. In this paper we propose a method of SPICE-compatible thermal simulation for interconnect reliability analysis. The lumped thermal circuit modeling with adaptive approach is used to reduce the problem size. The improved extended Krylov subspace (IEKS) method, independent of the number of input ports, is used for thermal simulation. The experimental results show that our method provides highly accurate results with performance improvement 15 x over T-Spice for the problem with node number 72428.

Abstract: PROBLEM TO BE SOLVED: To solve the problem that the life becomes short for a chip that is most heavily stressed by the electric field in a nonvolatile memory cell and the memory reliability deteriorates because the electric field stress changes on the capacitor insulation film or the tunneling insulation film due to the variations in the process even if the power source voltage is kept constant. SOLUTION: A capacitive coupling rate measuring circuit 107 is provided in a chip. When electrically testing a chip, first testing is made in DC by using a regular power supply, then the capacitive coupling rate is measured. And the correction value is set for the power supply voltage depending on the measured capacitive coupling rate. Then the regular memory test is carried out. After shipping as the products, various operations are performed by using the corrected power supply voltage. Variations in the memory cell process in the manufacturing steps are absorbed by correcting the power supply voltage with converting the variations into the equivalent capacitive coupling rate. Thus, the reliability is markedly improved for the electric field stress while extending the life of the chip. COPYRIGHT: (C)2004,JPO

Abstract: To suppress enlargement of the chip size, and improve the reliability in interlayer connections. Grooves 4 a - 4 c are provided at positions of scribe lines SL of semiconductor substrates 1 a - 1 c ; and conductive material 11 is filled in the grooves 4 a - 4 c provided in sections of the semiconductor substrates 1 a - 1 c after the semiconductor substrates 1 a - 1 c are stacked in layers.

Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms. Alternatively, the invention enables adaptive adjustment of the operating frequency of an integrated circuit. The invention enables system designers to adaptively optimize either system performance or power consumption on a part-by-part basis in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

Abstract: The present invention relates to electronic circuits that retain identical functionality and performance under RAM and hard-wire ROM fabrication options. An integrated circuit (IC) providing identical functionality and performance in two selectable fabrication options, wherein: a first selectable option comprises a user configurable circuit; and a second selectable option comprises a hard-wired circuit in lieu of said user configurable circuit. Such a programmable to hard-wire conversion provides a significant IC cost reduction at minimal NRE cost and improved reliability.

Abstract: A study has been conducted to quantify the ability of spray cooling to handle transient die power dissipation, as well as to quantify its effect on device reliability. The transient study was conducted with a bare die thermal test vehicle, while the device reliability studies were conducted with a dual Opteron Compact PCI single board computer. For the transient response studies, the high heat transfer coefficients associated with the spray cooling enabled the die to transition from one steady-state point to another in under 2 seconds, when cycling the power delivered to the die between 0 and 94 W. For the device reliability studies, an air-cooled version of the server board was compared to a spray cooled version, for the same clock frequency and supply voltages. For identical conditions, the spray cooled microprocessor processor diode temperature was 33.3/spl deg/C lower, and the die dissipated 35% less power. The paper will present an analysis that explains the manner in which modern microprocessors operate, and will explain the reason for the higher power dissipation associated with the hotter microprocessor.

Abstract: Reliability of power supply is related, among other factors, to the control and protection devices allocation in feeders of distribution systems. In this way, optimized allocation of sectionalizing switches and protection devices in strategic points of distribution circuits, improves the quality of power supply and the system reliability indices. In this work, it is presented a mixed integer nonlinear programming (MINLP) model, with real and binary variables, for the sectionalizing switches and protection devices allocation problem, in strategic sectors, aimed at improving reliability indices, increasing the utilities billing and fulfilling exigencies of regulatory agencies for the power supply. Optimized allocation of protection devices and switches for restoration, allows that those faulted sectors of the system can be isolated and repaired, re-managing loads of the analyzed feeder into the set of neighbor feeders. Proposed solution technique is a genetic algorithm (GA) developed exploiting the physical characteristics of the problem. Results obtained through simulations for a real-life circuit, are presented.

Abstract: A new approach for dynamic reliability and power management of integrated systems, such as systems on chips (SoCs) and networks in chips (NoCs) is presented. With aggressive transistor scaling, decreased voltage margins, and increased processor power and temperature, reliability assessment has become a significant issue in design. Our work combines for the first time dynamic power management with reliability models. The joint model is used to determine system level reliability as a function of failure rates, system configuration and power management policies. We show that the overall system reliability is strongly affected by reliability network topology and power management policy.

Abstract: Reliability extrapolation of ultrathin (EOT