Showing papers on "Reliability (semiconductor) published in 2003"
TL;DR: The Pain Assessment in Advanced Dementia (PAINAD) scale is a valid and reliable tool for measuring pain in noncommunicative patients with advanced dementia.
Abstract:
Objectives
To develop a clinically relevant and easy to use pain assessment tool for individuals with advanced dementia that has adequate psychometric properties.Design
Instrument development study using expert clinicians and behavioral observation methods. Measurement of sensitivity of the instrument to detect the effects of analgesic medications in a quality improvement activity.Setting
Inpatient dementia special care units in a Veterans Administration Medical Center.Participants
Nineteen residents with advanced dementia who were aphasic or lacked the ability to report their degree of pain and six professional staff members. Additionally, data from medical records of 25 residents who were receiving pain medications as required (PRN) were collected.Measurements
Based on the literature review, related assessment tools and consultation with expert clinicians, a five-item observational tool with a range of 0 to 10 was developed. The tool, Pain Assessment in Advanced Dementia (PAINAD), was compared with the Discomfort Scale and two visual analog scales (discomfort and pain) by trained raters/expert clinicians in the development study, and used for detection of analgesic efficacy in a quality improvement activity.Results
Adequate levels of interrater reliability were achieved between dyads of the principal investigator with each clinical research rater and between two raters. PAINAD had satisfactory reliability by internal consistency with a one factor solution. PAINAD and the Discomfort Scale–Dementia of Alzheimer Type (DS-DAT) were significantly correlated, providing evidence of construct validity. PAINAD detected statistically significant difference between scores obtained before and after receiving a pain medication.Conclusions
The PAINAD is a simple, valid, and reliable instrument for measurement of pain in noncommunicative patients. Since the patient population used for its development and testing was limited to a relatively small number of males, further research is needed before it can be universally recommended.658 citations
12 Oct 2003
TL;DR: In this paper, an online junction temperature estimation and manipulation of the switching frequency and current limit to regulate the losses are used to prevent overtemperature and power cycling failures in insulated gate bipolar transistor (IGBT) power modules.
Abstract: Active thermal control techniques make it feasible to regulate the steady state and transient thermal-mechanical stress in power electronic modules for applications such as motor drives. Online junction temperature estimation and manipulation of the switching frequency and current limit to regulate the losses are used to prevent overtemperature and power cycling failures in insulated gate bipolar transistor (IGBT) power modules. The techniques developed in this work are used to actively control the junction temperature of the power module. This control strategy improves power module reliability and increases utilization of the silicon thermal capacity by providing sustained operation at maximum attainable performance limits.
321 citations
23 Jun 2003
TL;DR: In this paper, the authors present a methodology for evaluating the impact of DG units installation on electric losses, reliability and voltage profile of distribution networks based on a power flow method with the representation of generators as PV buses.
Abstract: This work presents a methodology for evaluating the impact of DG units installation on electric losses, reliability and voltage profile of distribution networks. The losses and voltage profile evaluation is based on a power flow method with the representation of generators as PV buses. The reliability indices evaluation is based on analytic methods modified to handle multiple generations. The methodology may be used to evaluate the influence of the local of installation and the capacity of DG on these system performance characteristics for different generation expansion planning alternatives. The results obtained with the proposed methodology for systems extracted from the literature demonstrates its applicability.
209 citations
TL;DR: In this paper, an extension of reliability analysis of electronic devices with multiple competing failure modes involving performance aging degradation is presented, where the probability that a product fails on a specific failure mode is derived.
Abstract: This paper presents an extension of reliability analysis of electronic devices with multiple competing failure modes involving performance aging degradation. The probability that a product fails on a specific mode is derived. Using this probability, the dominant failure mode on the product can be predicted. A practical example is presented to analyze an electronic device with two kinds of major failure modes–solder/Cu pad interface fracture (a catastrophic failure) and light intensity degradation (a degradation failure). Reliability modeling of an individual failure mode and device reliability analysis is presented and results are discussed. Copyright © 2003 John Wiley & Sons, Ltd.
150 citations
TL;DR: The results of tests on a number of commercial Smartpack ® modules provide useful information about the influence of materials properties and geometry on the step response, and could be used for package quality control and reliability investigations.
112 citations
Abstract: Abstract On-farm welfare-assessment protocols should be based on valid, reliable and feasible indicators which reflect the animal's state in the context of the housing and management system. This paper focuses on the selection of parameters for cattle and buffalo from welfare research, from assessment protocols used in different European countries and from the literature. Three groups of parameters are described: (1) parameters which can readily be included, such as lameness, injuries, body condition score, cleanliness, getting up/lying down behaviour, agonistic social behaviour, oral abnormal behaviours, human behaviour toward the animals and measures of the animal-human relationship; (2) parameters which require more information on reliability, such as indicators of good welfare and housing factors; and (3) parameters which are regarded as important but so far lack reliability in most countries, such as the incidence of clinical diseases and mortality.
112 citations
TL;DR: The SP100 space nuclear reactor was designed for use as an orbital power supply, lunar or Martian surface power station, and power supply for nuclear electric propulsion, with a scaleable power range of 10's kWe to 100'skWe.
81 citations
Patent•
8 Jan 2003TL;DR: In this paper, a measuring device incorporating a substrate with sensors that measure the processing conditions that a wafer may undergo during manufacturing is presented, where the substrate can be inserted into a processing chamber by a robot head and the measuring device can transmit the conditions in real time or store the conditions for subsequent analysis.
Abstract: A measuring device incorporating a substrate with sensors that measure the processing conditions that a wafer may undergo during manufacturing. The substrate can be inserted into a processing chamber by a robot head and the measuring device can transmit the conditions in real time or store the conditions for subsequent analysis. Sensitive electronic components of the device can be distanced or isolated from the most deleterious processing conditions in order increase the accuracy, operating range, and reliability of the device.
68 citations
8 Dec 2003
TL;DR: The notion of self-consistent solutions of die temperature in estimating the die temperature for sub-100 nm CMOS technologies by taking into account various electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature is introduced.
Abstract: Accurate estimation of the silicon junction (or die) temperature in high-end microprocessors is crucial for various performance analyses and also for chip-level thermal management This work introduces for the first time, the notion of self-consistency in estimating the die temperature for sub-100 nm CMOS technologies by taking into account various electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature It also comprehends chip-level reliability constraints and the impact of employing various packaging and cooling solutions in an integrated manner The self-consistent solutions of die temperature are shown to have significant implications for evaluating various power-performance-reliability-cooling cost tradeoffs and can be used to optimize the performance of nanoscale ICs
65 citations
64 citations
1 Dec 2003
TL;DR: In this paper, the reliability issues of two-bit storage nitride flash memory cells, including low-V/sub t/state threshold voltage instability, read-disturb, and high V/sub T/state charge loss are addressed.
Abstract: The reliability issues of two-bit storage nitride flash memory cells, including low-V/sub t/ state threshold voltage instability, read-disturb, and high-V/sub t/ state charge loss are addressed The responsible mechanisms and reliability models are discussed Our study shows that the cell reliability is strongly dependent on operation methods and process conditions
TL;DR: In this article, a low frequency measurement set-up was developed to test capacitive RF MEMS switches for reliability and lifetime testing, and the principle of operation was described, as well as measurements revealing the following failure modes of the switches: stiction of the bridge of the devices under test due to charging and breakdown of the dielectric.
Abstract: The reliability and lifetime testing of capacitive RF MEMS switches one by one at the intended signal frequency range (GHz) is very expensive because RF equipment is monopolized for a large amount of time. Testing a statistically significant number of devices in this way is therefore impractical. Furthermore testing the switches in a harsh environment is difficult. We have developed a new, low frequency measurement set-up to address these issues. In this paper, the principle of operation is described, as are measurements revealing the following failure modes of RF MEMS switches: stiction of the bridge of the devices under test due to charging, and breakdown of the dielectric. We also show that the system can be used to monitor other characteristics, such as the rise- and fall-times and incomplete pull-in of the bridge of the switch when actuated.
TL;DR: Diode failures are a limiting factor for the reliability of power circuits and one failure reason is dynamic avalanche, Dynamic avalanche can be distinguished in three degrees, and some designs are ruined.
Patent•
16 Dec 2003TL;DR: In this article, the data are classified according to their desired lifetime and then archived in a memory using a storage method whose reliability is in accordance with the desired lifetime, which is a method and system for archiving data.
Abstract: A method and system for archiving data. The data are classified according to their desired lifetime and then archived in a memory using a storage method whose reliability is in accordance with the desired lifetime. For example, when storing data in the cells of an EPROM, short-term data could be archived using larger programming voltage pulse increments than for long-term data, using a lower target threshold voltage than for long-term data, using wider programming voltage pulses than for long-term data, using higher starting programming voltages than for long-term data, using fewer programming voltage pulses than for long term data, using lower maximum programming voltages than for long term data, or using more levels per cell than for long-term data.
Patent•
19 Mar 2003
TL;DR: In this article, a control method and arrangement that monitors the condition and operating parameters of a power electronic system having power electronic devices and responds to various detected abnormalities to optimize operation of the power electronic systems is presented.
Abstract: A control method and arrangement that monitors the condition and operating parameters of a power electronic system having power electronic devices and responds to various detected abnormalities to optimize operation of the power electronic system The arrangement increases reliability of operation and optimizes the continuous supply of power to a load The arrangement also includes the capability for diagnosing the parameters of the power electronic switches including drive current, drive voltage and operating temperature and for communicating the status information in a coordinated fashion
8 Dec 2003
TL;DR: In this paper, the authors review the status of reliability studies of high-k gate dielectrics and show that the reliability properties of such materials are influenced both by the interfacial layer as well as the high k layer.
Abstract: High-k gate dielectric materials are likely to be implemented in Si CMOS processes in the near future Reliability characteristics that closely match, or exceed, those of SiO/sub 2/ will be one of the primary goals of future development work In this paper we review the status of reliability studies of high-k gate dielectrics High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fixed charge The reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer Attainment of reliability goals will require elimination of charging effects, which dominate transistor degradation
TL;DR: In this paper, the long-term stability of AlGaAs/GaAs and InAlAs/InGaAs high electron mobility transistors (HEMTs), tested under high drain voltage and/or high temperature operation, is reported.
Abstract: The long-term stability of AlGaAs/GaAs and InAlAs/InGaAs high electron mobility transistors (HEMTs), tested under high drain voltage and/or high temperature operation is reported. HEMTs with high In content in the active channel, alternatively fabricated on InP substrates and on GaAs substrates covered by a metamorphic buffer (MHEMT), are compared. Despite the high dislocation density in the buffer layer MHEMTs and InP based HEMTs exhibit comparable reliability. AlGaAs/GaAs HEMTs are more reliable than their InAlAs/InGaAs counterparts, especially when operated at high drain voltage. Failure mechanisms are thermally activated gate sinking, Ohmic contact degradation and hot electron induced degradation.
8 Dec 2003
TL;DR: In this paper, the impact of bias temperature degradation on logic product speed and operating voltage was investigated, and a reliability guardband was recommended as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime.
Abstract: This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product speed (F/sub max/) and minimum allowed operating voltage (V/sub ccmin/). Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanisms and models are proposed to explain the interaction of fluorine with device and circuit reliability. A reliability guardband in F/sub max/ and V/sub ccmin/ is recommended as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime.
Patent•
24 Jun 2003TL;DR: In this paper, the back surface of the upper semiconductor chip is polished, the entire side surfaces are covered with a resin layer, or the center portion of the semiconductor chips is formed to be thicker than the peripheral portion thereof.
Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.
Patent•
28 Jul 2003TL;DR: In this article, a gate voltage detector that detects a gate-emitter voltage Vge that appears between the gate and emitter of a power semiconductor device throughout a detection time period is presented.
Abstract: A drive circuit includes a gate voltage detector that detects a gate-emitter voltage Vge that appears between the gate and emitter of a power semiconductor device throughout a detection time period during which a sampler allows the process of detecting the gate-emitter voltage Vge, and that recognizes the occurrence of an abnormality in the power semiconductor device when the gate-emitter voltage Vge exceeds a reference value. Therefore, the drive circuit can protect the power semiconductor device with higher reliability by promptly detecting the occurrence of a short circuit even when the power semiconductor device is resistant to high voltages.
Patent•
8 Aug 2003
TL;DR: In this paper, the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second chip is significantly larger than the first chip.
Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip. Therefore, it becomes possible to prevent the occurrence of microcracks in the second semiconductor chip and to prevent the occurrence of defective fine metal wire connections caused by the impact at the time of electrical connection of the second semiconductor chip to the wiring board.
Patent•
IBM1
TL;DR: In this article, a number of performance parameters for an electronic system are determined at a particular age of the electronic system, and the performance parameters can be correlated to maximum operating frequency of electronic components for the particular age.
Abstract: A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
Patent•
31 Dec 2003TL;DR: In this paper, the authors present an on-chip frequency compensation circuit that includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillators to generate an AC degraded signal, and a static frequency oscillator, coupled with a compare circuit coupled to the oscillators, compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
Abstract: Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
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TL;DR: This paper presents a general discussion of the reliability limiting mechanisms that can impact RF MEMS devices, with an emphasis on the issues relevant to RF switch cycling lifetimes.
Abstract: Device reliability is a key factor in the ultimate insertion of RF MEMS devices into operational systems. In particular, cycle lifetimes of contacting devices such as RF switches can be technically challenging due to the requirement of good contact electrical performance under operational stresses. This paper presents a general discussion of the reliability limiting mechanisms that can impact RF MEMS devices, with an emphasis on the issues relevant to RF switch cycling lifetimes.
Patent•
3 Oct 2003TL;DR: In this paper, the authors proposed a manufacturing method for a semiconductor device having an MCP structure in which a plurality of semiconductor chips are internally provided in a single package and its manufacturing method, wherein the semiconductor chip requiring burn-in can be ensured of initial reliability while the other chip requiring no burnin could be protected against damage.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having an MCP structure in which a plurality of semiconductor chips are internally provided in a single package and its manufacturing method, wherein the semiconductor chips requiring burn-in can be ensured of initial reliability while the other semiconductor chips requiring no burn-in can be protected against damage. SOLUTION: The manufacturing method comprises a first process (steps 30 to 32) of sealing up the semiconductor chips requiring burn-in with resin to package them and making the packaged semiconductor chips undergo burn-in, and a second process (step 36) of mounting the semiconductor chips which are judged non-defective in burn-in on a board together with the semiconductor chips requiring no burn-in. COPYRIGHT: (C)2004,JPO
2 Nov 2003
TL;DR: A high power density, high reliability SRM design for aerospace applications in line with the more electric aircraft initiative that has been in place for many years and aims at utilizing electric power to drive subsystems in aerospace applications.
Abstract: Switched reluctance machines (SRMs) have been extensively researched for mission critical high performance applications due to their high reliability, performance, fault-tolerance and high power densities. This paper discusses a high power density, high reliability SRM design for aerospace applications. This is in line with the more electric aircraft initiative that has been in place for many years and aims at utilizing electric power to drive subsystems in aerospace applications. These electric subsystems are intended to replace the historical hydraulic, pneumatic and mechanical power transfer systems, leading to better performance and efficiencies. The machine design is verified using commercially available 2-D and 3-D finite element analysis (FEA) software. A dynamic simulator program to verify the operation of the machine using an asymmetric bridge converter is designed and developed, and results of the simulator are included.
TL;DR: It is concluded that silicon dioxide-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50 nm technology node using silicon-dioxide-based gate insulators.