Abstract: Since a couple of decades ago, voltage stability assessment has received increasing attention due to the complexity of power systems. With the increase in power demand and limited power sources has caused the system to operate at its maximum capacity. Therefore, a study that is able to determine the maximum capacity limit before voltage collapse must be carried out so that necessary precaution can be taken to avoid system capacity violation. This paper presents a novel fast voltage stability index (FVSI) simplified from a pre-developed voltage stability index referred to a line initiated from the voltage quadratic equation at the sending end of a representation of a 2-bus system. The line index in the interconnected system in which the value that is closed to 1.00 indicates that the line has reached its instability limit which could cause sudden voltage drop to the corresponding bus caused by the reactive load variation. The formulated index was tested on the IEEE reliability test system in order to verify the performance of the proposed indicator. Results showed that the proposed technique is indicative in predicting the occurrence of system collapse and hence necessary action can be taken to avoid such incident.

Abstract: The present understanding of wear-out and breakdown in ultrathin (t/sub ox/ < 5.0 nm) SiO/sub 2/ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.

Abstract: 1 BCD Technologies for Smart Power ICs.- 2 Technologies for High Voltage ICs.- 3 Smart Discrete Technologies.- 4 Dielectric Isolation Technologies and Power ICs.- 5 Power Mosfets Driving Circuits and Protection Techniques.- 6 Motion Control.- 7 Switching Regulators.- 8 High Voltage Integrated Circuits for Off-Line Power Applications.- 9 Automotive Electronics.- 10 Audio Amplifiers.- 11 High Complexity Smart Power Devices and Future Developments.- 12 Modeling, Design and Simulation of Power Electronic Devices and Circuits.- 13 Packaging.- 14 Reliability of Smart Power ICs.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in the form of a chip size package which can reliably connect a semiconductor chip and an interposer substrate with a high reliability SOLUTION: In connection between a semiconductor chip 10 having an electrode 11 and an interposer substrate 12, an anisotropic conductive film 13 wherein resin particles 22 are disposed is disposed between the chip and substrate and heated to form a junction thereof

Abstract: For Part I see ibid, vol49, no2, pp232-8 (2002) Based on the theory of soft and hard breakdown established in Part I of this paper, we now study the principles of area, thickness, voltage, and circuit configuration dependence of hard and soft breakdown These scaling principles allow us to conclude that breakdown in ultrathin oxides stressed at operating voltages (10-15 V) can never be hard, which should allow a more relaxed reliability specification for these oxides

Abstract: Oxide wearout, breakdown, and reliability, D.J. Dumin reliability of flash nonvolatile memories, N. Mielke and J. Chen physics and chemistry of intrinsic time-dependent dielectric breakdown in SiO2 dielectrics, J.W. McPherson breakdown modes and breakdown statistics of ultrathin SiO2 gate oxides, J. Sune et al MOSFET gate oxide reliability - anode hole injection model and its applications, Y.-C. Yeo et al.

Abstract: A method and structure tests devices on a wafer by applying an electrical bias to the devices and simultaneously monitoring emitted light from all of the devices. The emitted light indicates locations of defective devices and records time-based images of the emitted light across the wafer.

Abstract: Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

Abstract: This paper discusses the effective and potential advantages/drawbacks of Raman micro-spectrometry technique. The procedures to improve the sensitivity, the legibility and the reliability will be addressed. Examples will be chosen among fibre-reinforced ceramic, polymer or metal matrix composites.

Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.

Abstract: Bias temperature degradation is studied in p-MOSFETs. The physical mechanisms responsible for degradation over a wide range of stress bias and temperature have been identified. A novel scaling methodology is proposed that helps in obtaining a simple, analytical model useful for reliability projection.

Abstract: A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.

Abstract: The growing concern about wide area power system disturbances and their impact on power systems have reinforced interest in the new generation of system protection tools. Their application depends on their reliability, which, in turn, depends on the reliability of the hardware infrastructure on which they rely. In this paper, we propose a modification of a Voltage Instability predictor, proposed some time ago. The modification provides a path for integration of a stand-alone, local protection devices with a potential system-wide action, and takes into account the voltage characteristics of the loads.

Abstract: Bulk-power systems are fundamentally different from other Permitting and large infrastructure systems, such as air-traffic control centers, natural-gas least some re pipelines, and long-distance telephone networks. Electric systems to face til have two unique characteristics: . . Need for continuous and near electricity pl instantaneous balancing of geneconomic, ei eration and load, consistent with transmission-network conand reliabi straints Because the transmission network is largely passive, controlling flows on individual lines is limited primarily to adjusting generation output and to opening and closing switches to add or remove transmission lines from service. Because of these two characteristics, bulk-power system operators rely primarily on changes in generation output (MW movements up or down) to keep the system in balance and comply with transmission limits. In principle, changes in electricity consumption could serve as well as generator movements in meeting these reliability requirements, but the use of customer loads for reliability purposes is the exception rather than the rule. The traditional, vertically integrated utility managed short-term reliability by dispatching its generating units as well

Abstract: MEMS switch technology represents a key enabling element for advanced RF systems. These devices provide extremely low loss, high linearity, and broad bandwidth relative to traditional semiconductor switches. A significant impediment to fully realizing these benefits in deployed systems is their reliability under high cycle numbers. Due to their low force actuation and multi-physics operation, the reliability of MEMS contact switches may be impacted by a broad range of different mechanisms. Thus, a key component of the reliability improvement process is the separation and identification of reliability-limiting processes. A number of experimental methods have been developed to support these determinations, and the application of one permitting contact response measurement is presented.

Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

Abstract: The present invention proposes a light-guiding plate module of high reliability to provide a required uniform light source for a display. The light-guiding plate module comprises a single or at least two light-transmitting plates. Each light-transmitting plate comprises an upper and a lower light-guiding uniform plates. A light-focusing pattern and a light-intercepting pattern are formed on the upper and lower light-guiding uniform plates, respectively. At least a light-emitting source is disposed at least at a side of the light-transmitting plate. The light-guiding plate module of the present invention provides a light source of super-high brightness and good reliability for an LCD to apply to displays of control boards in cockpits of various kinds of vehicles.

Abstract: The demands for electronic packages with lower profile, lighter weight, and higher input/ output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent demand high I/O density and good reliability characteristics have led to the evolution of ultra high-density non-solder interconnection, such as wire interconnect technology (WIT). New technology, which uses copper posts to replace the solder bumps as interconnections, has improved reliability. Moreover, this type of wafer level package produces higher I/O density, as well as ultra fine pitch. This research focuses on the reliability analysis, material selection and structural design of WIT packaging. This research employs finite element method (FEM) to analyze the physical behavior of packaging structures under thermal cycling conditions to compare the reliability characteristics of conventional wafer level and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature-dependent material properties will be applied to all models. @DOI: 10.1115/1.1481368#

Abstract: Circuits are provided for increasing the reliability of an iontophoretic drug delivery system. Such circuits detect the failure of a crystal oscillator of the system, the failure of a voltage reference of the system, or the impending failure of a battery power source of the system.

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract: PROBLEM TO BE SOLVED: To a semiconductor device which can be directly, electrically connected with a printed wiring board without interposing a lead component SOLUTION: A transition layer 38 is placed on a die pad of IC chip 20 to be incorporated in a multi-layer printed wiring board 10 Thereby, an electrical connection between the IC chip 20 and the multi-layer printed wiring board 10 may be obtained without using any lead component and sealing resin Additionally, a residual resin on a pad 24 can be avoided by locating the copper transition layer 38 on the die pad 24, and a connectivity between the die pad 24 and a via hole 60 and its reliability may be improved

Abstract: As process technologies continue to scale, the effects of temperature can no longer be neglected. High on-chip temperature causes frequency degradation, increases wasteful leakage power, and lowers device reliability. Therefore, managing on-chip temperature becomes an important design undertaking. In this brief, the effects of temperature on very large-scale integration design are presented, and an analytical technique is introduced to systematically design and evaluate thermal control mechanisms, such as the dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS). Using the energy-delay product (EDP) metric, the DFS is shown to outperform the DCT.