TL;DR: The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed in this article, where factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance are discussed.
Abstract: The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.
TL;DR: In this paper, an induction heating and control system and method have enhanced reliability and advanced performance features for use with induction cooking devices, such as induction heating ranges, which are facilitated via the use of an inductive heating system which integrates voltage management, power management, thermal management, digital control sensing and regulation systems, and protection systems management.
Abstract: An induction heating and control system and method have enhanced reliability and advanced performance features for use with induction cooking devices, such as induction heating ranges. Enhanced performance is facilitated via the use of an induction heating system which integrates voltage management, power management, thermal management, digital control sensing and regulation systems, and protection systems management.
TL;DR: It is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations.
Abstract: This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.
TL;DR: In this paper, a random search algorithm based on power system heuristics is given for fast rare-event simulation of consecutive relaying malfunctions in bulk power systems and an economical system upgrading strategy that can best enhance the protection system reliability under limited budget.
Abstract: Recent studies have shown that hidden failures in the protective devices have a great impact on the power system reliability. In this paper, the authors provide definitions of vulnerability and reliability of protection systems to numerically characterize this impact. A random search algorithm based on power system heuristics is given for fast rare-event simulation of consecutive relaying malfunctions in bulk power systems. They also propose an economical system upgrading strategy that can best enhance the protection system reliability under limited budget. Finally, they present the result of a case study on New York Power Pool (NYPP) 3000-bus system.
TL;DR: In this paper, the Weibull process is used to model the life cycle of a jet engine and the removal characteristics are estimated by collecting actual field data based on the engine age and operating environment.
TL;DR: In this article, the size, weight, power rating, availability and reliability of electrical power systems are important for future weapons systems, including advanced vehicles and systems; potential new weapons; and man-portable or alternative power.
Abstract: The size, weight, power rating, availability and reliability of electrical power systems are important for future weapons systems. Applications could include: advanced vehicles and systems; potential new weapons; and man-portable or alternative power. Over twenty R&D studies in pulsed power have been initiated by IAT for the US Army over the last three years. Highlights of some developments in rotating machines and pulse-forming network (PFN) components are described.
TL;DR: A simple measure called unit level predicted yield, based on the yield of other die in the same fab lot, is developed and shown to be approximately twice as efficient as wafer level methods at highlighting die with high latent defect density.
Abstract: Previous studies have demonstrated both theoretically and empirically that defect density at wafer sort is an effective predictor of burn-in failures on packaged semiconductor devices. Therefore, efficient methods of measuring sort defect density are of great interest. This paper explores optimal methods for measuring sort defect density at the die level, as opposed to the lot or wafer level, and using this measure to screen reliability defects. The authors developed a simple measure called unit level predicted yield, based on the yield of other die in the same fab lot, and demonstrated its strong correlation to burn-in failures on packaged units. The method makes physical sense, and has been validated on more than 80 million units on three fab processes, including Intel's 0.8 /spl mu/m, 6 layer metal CMOS logic process. It is applicable to known good die programs, or anywhere that die level reliability differentiation is desirable. It is shown to be approximately twice as efficient as wafer level methods at highlighting die with high latent defect density.
TL;DR: VFD-induced motor shaft voltage can significantly impact bearing life. This paper quantifies the damage and presents mitigation techniques.
Abstract: Motor bearing life historically has been difficult to predict. Many variables influence bearing life in motors, including operating speed, mechanical fit, loading, lubrication, vibration, and environmental conditions. A large synthetic fibers producer discovered that motor shaft voltage induced by variable-frequency drives (VFDs) can add another significant variable to the formula. Based upon this experience, this paper presents theory, test data, and actual results quantifying electrical discharge machining damage to bearings initiated by VFDs. The paper presents several mitigation techniques and quantify their relative effectiveness and attributes. Other factors and interactions of the above-mentioned variables are also discussed in relation to the total goal of improving motor bearing life.
TL;DR: In this paper, customer confidence in the longterm reliability of MEMS (also known as microsystems or micromachines) under diverse stringent conditions has been demonstrated for pressure sensor, accelerometer, display, and printing applications.
Abstract: Microelectromechanical systems (MEMS) devices are being manufactured in the hundreds of millions and are widely deployed for pressure sensor, accelerometer, display, and printing applications. This suggests customer confidence in the longterm reliability of MEMS (also known as microsystems or micromachines) under diverse stringent conditions.
TL;DR: In this paper, a pair of pressure sensors are mounted upon a single pressure sensor diaphragm and compared, and if the difference between the signals exceeds a predetermined threshold, it is determined that a malfunction of the pressure sensor has ocurred.
Abstract: The reliability of a pressure sensor is improved either by utilization of redundant composants. A pair of pressure sensors are mounted upon a single pressure sensor diaphragm. The pressure signals generated by the pressure sensors are compared and, if the difference between the signals exceeds a predetermined threshold, it is determined that a malfunction of the pressure sensor has ocurred. Alternately, additional diagnostic testing may be included to detect a malfunctioning sensor.
TL;DR: In this paper, the advantages of transitioning to copper/low-k interconnects are discussed and reliability concerns associated with such devices are highlighted, and the material and process challenges during the fabrication of devices with copper and low-k interfaces are discussed.
Abstract: Copper/low-k dielectric materials have been rapidly replacing conventional aluminum-alloy/SiO2-based interconnects in today’s semiconductor devices. This paper reviews the advantages of transitioning to copper/low-k interconnects. Materials and process challenges during the fabrication of devices with copper/low-k interconnects are discussed. Reliability concerns associated with such devices are highlighted.
TL;DR: In this paper, the authors proposed a voltage-controlled oscillator (VCO) that uses a differentially tunable impedance, rejecting commonmode noise (undesirable voltage variations that affect both control voltages) and thus bolsters reliability of communication circuits.
Abstract: Many electronic devices, such as computers and printers, communicate data to each other over wireline or wireless communications links. One component vital to such communications is a voltage-controlled oscillator (VCO)—a circuit that outputs an oscillating signal having an oscillation frequency based on a control voltage. Conventional VCOs adjust frequency based on a single control voltage input, which makes them vulnerable to unintended changes in the control voltage (and power-supply voltages relative to the control voltage.) These voltage changes cause frequency deviations that can make communications between devices less reliable. Accordingly, the present inventors devised a VCO that includes differential frequency control—frequency control based on the difference of two control voltages. The VCO, which uses a differentially tunable impedance, rejects common-mode noise (undesirable voltage variations that affect both control voltages) and thus bolsters reliability of communication circuits, such as phase-lock loops, receivers, transmitters, transceivers, and other devices that use it
TL;DR: In this paper, a physically-based model for reliability analysis of flash memories is presented, which provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current.
Abstract: A new physically-based model for reliability analysis of flash memories is presented. The model provides a quantitative description of the distribution of the stress-induced leakage current (SILC) in large memory arrays, considering the statistics of the defects responsible for the trap-assisted tunneling (TAT) current. Simulation results are in good agreement with SILC statistics over oxide thicknesses of 6.5, 8.8 and 9.7 nm. The model can be used to quantitatively evaluate the failure rate under different conditions and assess the trade-off between oxide thinning and device reliability. The relationship between tunnel oxide scalability and defect concentration is also quantitatively assessed.
TL;DR: This paper presents for the first time a rigorous coupled analysis of AC electromigration that are prevalent in signal lines and thermal effects arising due to Joule heating of the wires to suggest that for the optimally buffered interconnects, the current density in the vias exceeds the reliability limits and therefore requires careful consideration in the physical design process flow.
Abstract: In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. This paper presents for the first time a rigorous coupled analysis of AC electromigration that are prevalent in signal lines and thermal effects arising due to Joule heating of the wires. The analysis is applied to study the effect of technology scaling using ITRS data, wherein the effects of increasing interconnect (Cu) resistivity with line dimensions and the effect of a finite barrier metal thickness have been included. Finally, we have also quantified the reliability implications for minimum sized vias in optimally buffered signal nets. Our analysis suggests that for the optimally buffered interconnects, while the maximum current density in the line remains limited by the performance, the current density in the vias exceeds the reliability limits and therefore requires careful consideration in the physical design process flow.
TL;DR: In this paper, the authors proposed a method for manufacturing multilayer printed-wiring boards which incorporate semiconductor devices of high reliability, which can be found in the IC chip 20 and the via hole of the build-up layer.
Abstract: PROBLEM TO BE SOLVED: To propose a method for manufacturing multilayer printed-wiring boards which incorporate semiconductor devices of high reliability. SOLUTION: An IC chip 20 is placed so that a die pad 38 is in contact with a UV tape 40 and then filler 41 is filled. After that, the UV tape 40 is peeled off, and a build-up layer is formed in the IC chip 20, thus properly and electrically connecting the IC chip to the via hole of the build-up layer, and hence manufacturing multilayer printed-wiring boards incorporating reliable semiconductor devices.
TL;DR: The Chinese version of the Parenting Stress Index (S-PSI/SF) is a valid and reliable instrument for assessing parenting stress in Taiwanese parents of children with cancer.
Abstract: This study examined the psychometric properties of a Chinese version of the Parenting Stress Index/Short Form (PSI/SF). A 15-item simplified PSI/SF (S-PSI/SF) was subsequently developed which maintained a level of reliability and validity similar to the full version. The Chinese PSI/SF was tested on 149 parents (100 mothers, 49 fathers) of pediatric cancer patients in Taiwan. Psychometric testing was conducted using item analysis, Cronbach's alpha and confirmatory factor analysis. The S-PSI/SF was constructed based on the item analysis of the PSI/SF. Both the PSI/SF and S-PSI/SF produced good reliability coefficients. Confirmatory factor analyses indicated that both PSI/SF and S-PSI/SF met all criteria for goodness of fit. Compared with the PSI/SF, the S-PSI/SF demonstrated better internal consistency and overall fit at the one-subscale level, and satisfactory overall fit at two- and three-subscale levels. Despite the limited number of items included, the S-PSI/SF had a very good factor structure. No gender difference in parenting distress index was observed between mothers and fathers of pediatric cancer patients.The 15-item S-PSI/SF is a brief, easily administered instrument that has evidence of reliability and validity in Taiwanese parents of children with cancer. It could serve as a valuable assessment tool in clinical practice to identify parenting stress with a need for intervention.
TL;DR: In this paper, the development of the anode hole injection (AHI) model for reliability projection of the silicon dioxide gate dielectric is reviewed and the experimental and theoretical foundation of the AHI model is presented.
Abstract: We review the development of the anode hole injection (AHI) model for reliability projection of the silicon dioxide gate dielectric. The experimental and theoretical foundation of the AHI model is presented. Recent development and implications for the reliability of ultra-thin oxides are discussed. AHI is used to illuminate the questions of E versus 1/E models and field-driven versus voltage-driven models. Building on the concept of effective thinning, the AHI model is applied for the interpretation of defect-induced breakdown data and for optimizing oxide screening conditions. Circuit level reliability projection as a function of operating time, temperature, and power supply voltage is also illustrated.
TL;DR: In this paper, a simple theoretical model of heat conduction for short pulses with data from destruction time and energy measurements obtained during necessary destructive testing of integrated DMOS power switches is presented.
Abstract: Automotive power applications based on Smart Power ICs require the knowledge of dynamic DMOS temperature for optimum system design and reliability. An indirect method is presented here that combines a simple theoretical model of heat conduction for short pulses with data from destruction time and energy measurements obtained during necessary destructive testing of integrated DMOS power switches. The proposed "square root law" show a remarkable agreement with experimental data as well as with more complex thermal simulation results.
TL;DR: In this article, a set of thermo-mechanical tests has been applied to gas sensors based on silicon micromachined structures with dielectric membranes to determine the survivability of the devices under aggressive conditions of use.
Abstract: Thin film semiconductor gas sensors fabricated on thermally isolated silicon substrates have been proposed as good alternative to thick film devices that are on the market as they show low power consumption However, for their industrial success, it is necessary to assess good yield and high reliability for maintaining the functionality of the device during a long period of time In this paper, a set of thermo-mechanical tests has been applied to gas sensors based on silicon micromachined structures with dielectric membranes The aim of the tests is to determine the survivability of the devices under aggressive conditions of use The tests have been carried out on two specific structures, a single Si 3 N 4 membrane; and the same device that also includes a silicon plug below the sensor active area Results are compared as a tool for improving the structure in the future
TL;DR: In this article, the authors examine several important experimental aspects concerning ultrathin oxide reliability, including the statistical nature of breakdown measurements and the impact on data interpretation, and investigate the voltage-dependent voltage acceleration using two independent experimental methods over a wide range of oxide thickness values.
Abstract: In this paper, we critically examine several important experimental aspects concerning ultrathin oxide reliability. The statistical nature of breakdown measurements and the impact on data interpretation is discussed. Thickness dependence of Weibull slopes and its impact on reliability projection is reviewed. We also investigate the voltage-dependent voltage acceleration using two independent experimental methods over a wide range of oxide thickness values. Within the framework of a general defect generation model, we explore the possibility of a voltage-dependent defect generation rate to account for the increase in voltage acceleration with decreasing voltages. Using direct experimental results, we clarify that strong temperature dependence found on ultrathin oxides is a voltage effect, not a thickness effect as previously suggested, In the context of voltage-dependent voltage acceleration, we experimentally resolve various seemingly contradicting and confusing observations such as temperature-independent voltage acceleration and non-Arrhenius temperature dependence found on ultrathin oxides. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domain constructed from two important empirical principles based on comprehensive experimental database.
TL;DR: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chips 30 and a substrate, the semiconduct chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semicode chip 30 as discussed by the authors.
Abstract: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30 . Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chip 30 and a substrate, the semiconductor chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semiconductor chip 30 can be enhanced.
TL;DR: In this paper, a review of the SiGe HBTs for BiCMOS applications is presented, focusing on stability, reliability, simulation and material parameters, as well as their design, technology and performance.
Abstract: Extensive work has been done on the SiGe HBTs for BiCMOS applications recently. The work on stability, reliability, simulation and material parameters is critically examined and reviewed in this part of the review. The work on the design, technology and performance of the HBTs will be discussed in part II of the review.
TL;DR: The stability of the base dopant is the main reliability concern for heterojunction bipolar transistors (HBTs) and beryllium outdiffuses from the base into the emitter and causes device degradation.
TL;DR: In this paper, the strength and microstructure of the solder joints were examined after an exposure test at 398 K. The reaction layers formed at the interface between the solder and the Cu pad consisted of Cu 6 Sn 5 and Cu 3 Sn in the joints with Sn-10Pb plated Cu lead and consisted of only (Cu, Ni, Pd)6 Sn 5 in the joint with the Au/Pd/Ni plated CA lead after the exposure at 398 k up to 7.2 Ms for all five solders.
Abstract: QFPs (quad flat packages) with Sn-10Pb plated Cu lead or Au/Pd/Ni plated Cu lead were reflow-soldered using Sn-3.5 Ag, Sn-3Ag-5Bi, Sn-3.5Ag-0.7Cu, Sn-3.5Ag-2.5Bi-2.5In and Sn-37Pb solders. The strength and the microstructure of the solder joints were examined after an exposure test at 398 K. Although the strength of the solder joint with the Sn-10Pb plated Cu lead using the Sn-3Ag-5Bi solder significantly decreased with increasing holding time at 398 K, the strength of the other Sn-Ag based solder joints was comparable to that with the Sn-37Pb solder before and after the high temperature exposure test. The reaction layers formed at the interface between the solder and the Cu pad consisted of Cu 6 Sn 5 and Cu 3 Sn in the joints with Sn-10Pb plated Cu lead and consisted of only (Cu, Ni, Pd) 6 Sn 5 in the joints with the Au/Pd/Ni plated Cu lead after the exposure at 398 K up to 7.2 Ms for all five solders. The growth kinetics of the reaction layers obeyed the parabolic law except for the joint with the Sn-10Pb Plated Cu lead using the Sn-3Ag-5Bi solder, in which the growth of the reaction layer deviated from the parabolic law and accelerated beyond the holding time of 1.8 Ms. The unusual growth of the reaction layer, which resulted from a liquid phase forming ahead of the reaction layer and penetrating the grain boundaries of the reaction products, caused the degradation in the strength of this solder joint. The liquation was caused by the enrichment of Bi and Pb ahead of the reaction layer during the high temperature exposure to the extent where melting occur at the holding temperature above the Sn-Bi-Pb ternary eutectic point of about 370 K. The Sn-3Ag-5Bi solder is, therefore, considered to be unsuitable for assembling packages with the Sn-10Pb plated lead because of degradation in reliability during the high temperature exposure above 370 K.
TL;DR: In this article, the lifetime of the wiring connecting to the hole nearest to the bonding pad was improved by improving the reliability of the semiconductor device and reducing the length of the wires.
Abstract: The present invention aims at improving the lifetime of the wiring connecting to the hole nearest to the bonding pad and thereby improving the reliability of the semiconductor device. The invention relates to such semiconductor device and method of manufacturing the semiconductor device. The semiconductor device includes a plurality of first metal layers connected to a bonding pad, and plurality of aluminum wirings respectively connected to the first metal layers. The plurality of aluminum wirings are connected to a single second metal layer and have a length equal to or short than Blech Length.
TL;DR: In this article, the reliability problems of compound semiconductor transistors for microwave applications are reviewed, with the exception of the GaAs MESFETs, which exhibit a stable technology and an assessed reliability.
Abstract: This paper reviews the reliability problems of compound semiconductor transistors for microwave applications. These devices suAer from specific failure mechanisms, which are related to their limited maturity, with the exception of the GaAs MESFETs, which exhibit a stable technology and an assessed reliability. The metallizations employed in high electron mobility transistors (HEMTs) already benefit from this assessment. However, HEMT are aAected by concerns related to hot carriers and impact ionization. The trapping of carriers and the generation of defects in the diAerent layers are responsible for the observed instabilities. The stability of the base dopant is the main reliability concern for heterojunction bipolar transistors (HBTs). Beryllium outdiAuses from the base into the emitter and causes device degradation. Carbon has a lower diAusivity, but is aAected by the presence of hydrogen, which prompts gain variations. Finally the hot carriers reliability concern in SiGe HBTs is briefly reviewed. ” 2001 Elsevier Science Ltd. All rights reserved.
TL;DR: In this article, a new battery design is proposed for rectangular prismatic shaped batteries, which improves the reliability through the shaping of the batteries to reduce stresses on the electrochemical cells therein.
Abstract: A new battery design is provided. The design is applicable to rectangular prismatic shaped batteries, and improves the reliability through the shaping of the batteries to reduce stresses on the electrochemical cells therein, and the flexible packaging encapsulating the electrochemical cell.
TL;DR: In this paper, a preventive maintenance tool for shielded power cable systems based on the location of partial discharges is presented. But the diagnostic test method is limited in the sense that it does not cover all the locations of the discharges.
Abstract: Power cable systems can play a critical role with respect to the reliability of industrial plants. This paper reports on a preventive maintenance tool for shielded power cable systems based on the location of partial discharges. It describes the principles of the technology and provides data covering tests conducted on over 6000 km of medium voltage cables serving both electric utilities and industrial customers. It discusses the technical and economic advantages, as well as some of the limitations of the diagnostic test method.
TL;DR: In this paper, the authors proposed a method of manufacturing a semiconductor device of high reliability, where a wafer can be subjected to a lithography process, being kept in a good state even after the wafer on which a wiring metal layer of laminated structure is formed is stored for a long term.
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device of high reliability, where a wafer can be subjected to a lithography process, being kept in a good state even after the wafer on which a wiring metal layer of laminated structure is formed is stored for a long term. SOLUTION: In a step 11, transistor elements are formed on a semiconductor wafer, and a laminated wiring metal film composed of a prescribed wiring metal layer and an antireflection film or a barrier layer is formed on all the surface of a wafer. Being kept in this state, the semiconductor wafer is stored in a storehouse for a long term (step 12). The semiconductor wafer is taken out of the storehouse after an optional storage time, if necessary (step 13). Thereafter, as shown in a step 14, the semiconductor wafer delivered from a storehouse undergoes a rinsing process before the semiconductor wafer delivered from a storehouse is subjected to a lithography process. Thereafter, the semiconductor wafer is subjected to a lithography process in a step 15 for the formation of a required wiring pattern on the wafer.