Abstract: From the Publisher: This book is devoted entirely to flash memories and has been designed to provide comprehensive information on basic memory cell structures, device physics and technology, simulation circuit architecture, system issues, testing and reliability. It also provides data on advanced subjects related on multi-level storage cells, embedded memories and system applications of flash memories.

Abstract: Thermal barrier coating applications have been used on thermally loaded combustion process components for decades. In the beginning of turbine technology development, science and industry worked on solutions about how to combine different properties such as those of superalloy metals and ceramic insulators. While partially stabilized zirconia became the standard material very early on, thermal spraying and electron beam physical vapor deposition in the early 1990s were even considered as competing technologies. This paper reviews why EB-PVD is the actual choice for the latest state-of-the-art components. Although EB-PVD coatings have a higher thermal conductivity than plasma-sprayed coatings, especially for parts in the HP stage of the turbine, they have a longer life and are statistically more reliable. The major roadblocks for thermal barrier technology on its way to become a fully prime reliant, designed-in feature are the understanding and modeling of failure mechanisms and consequently to prove the developed lifing-models by testing and ultimately real component performance. Several potential answers for today's technical issues are discussed with respect to their ability to shift TBC applications to the next level of reliability within various engine environments. For example, the inline hardware concept offers a unique combination of conservative, proven process sequence steps with widely improved quality aspects and optimized throughput set-ups.

Abstract: Several alloy systems can be selected for high-temperature shape memory alloys, defined as alloys with stable reverse transformation temperatures above 120°C, However, due to the lack of minimum quality standards for stability, ductility, functional behavior and reliability, no successful applications have been realized so far. Research on high temperature shape memory alloys (HTSMA) is, nevertheless, an important topic not only for scientific reasons but also due to the market pull. This paper reviews existing systems of HTSMA pointing out their weak and strong parts.

Abstract: Existing literature indicates that there are two major mechanisms involved in the time dependent dielectric breakdown (TDDB) of silicon dioxide, and each mechanism dominates under different stress conditions. We suggest that the thermochemical (linear E) model and the hole-induced (1/E) model can be unified in one model. Based on the unified model, a wide range of TDDB data from different sources were examined and shown to behave consistently. Temperature and stress field dependencies are treated together in the model so that the lifetime is a single-valued function of temperature and field. The criterion for screen/ramp breakdown test is also discussed with the model. Furthermore, the unified model accounts for the effect of gross defects, which limit the oxide reliability in real ICs. The model is be used to predict the 10-year lifetime breakdown field or acceptable oxide thickness for a given voltage, and results suggest that further refinements for thin oxide (<5 nm) are necessary.

Abstract: The non-Arrhenius temperature dependence observed in the charge-to-breakdown data in thin oxides is related to the temperature dependence of the defect buildup in the same films For each temperature, this defect buildup is studied as a function of the defect generation probability and the total number of defects at breakdown Each of these quantities is shown to have its own unique temperature dependence, which when combined gives the results observed for the charge-to-breakdown data As the oxide layers are made thinner, the temperature dependence of the defect generation probability dominates these observations

Abstract: This paper presents a bibliography of papers on the subject of power system reliability evaluation. Papers in such areas as probabilistic load flow, probabilistic production costing, probabilistic transient stability evaluation etc. have not been included except where they specifically address power system reliability evaluation. It includes material which has become available since the publication of the five previous papers. "Bibliography on the Application of Probability Methods in Power System Reliability Evaluation", IEEE Trans. on Power Apparatus and Systems PAS-91, 1972, pp.649-60; PAS-97, 1978, pp.2235-42; PAS-103, 1984, pp. 275-82; IEEE Trans. on Power Systems, Vol. 3, No. 4, Nov. 1988, pp. 1555-64, and Vol. 9, No. 1, Feb. 1994, pp. 41-9.

Abstract: Electric-field and temperature acceleration models, such as the thermochemical breakdown (linear field dependence) model, the hole-induced breakdown (reciprocal field dependence) model, and the modified hole-induced breakdown model, are discussed. These models are examined; based on the results of long-term time-dependent dielectric breakdown (TDDB) tests over wide ranges of negative gate bias stress (8-13 MV/cm), test temperature (25, 75, and 125/spl deg/C), and oxide thickness (27-181 /spl Aring/). This was accomplished to confirm which model is applicable for thin oxide reliability, and to predict how TDDB in very thin oxide films occurs under a low-field stress for application to future generations of ULSI devices. With respect to the field acceleration dependence of the log-normal intrinsic breakdown at a high temperature of 125/spl deg/C, the thermochemical breakdown (linear field dependence) model yields the best fit when compared with other models, although it is difficult to make exact distinctions from long-term TDDB test results at 25/spl deg/C, even for several months. It is suggested that the thermochemical breakdown model is suitable as a field acceleration model for the TDDB phenomenon. The thermal activation energy and field acceleration parameter, based on the thermochemical breakdown model, exhibit linear dependencies. From the study of oxide thickness dependence between 27 and 181 /spl Aring/, the lifetime and failure rate of intrinsic oxide breakdown can be predicted for a given stress condition.

Abstract: The numerous advantages of insulated gate bipolar transistor (IGBT) power modules and their ongoing development for higher voltage and current ratings make them interesting for traction applications. These applications imply high reliability requirements. One important requirement is the ability to withstand power cycles. Power cycles cause temperature changes which lead to a mechanical stress that can result in a failure. Lifting of bond wires is thereby the predominant failure mechanism. A fast power cycling test method activating the main failure mechanism has been developed which allows to reproduce millions of temperature changes in a short time. The applicability of fast testing is supported by a mechanical analysis. Test results show the number of cycles to failure as a function of temperature changes for an IGBT single switch. A descriptive model is deduced from the results.

Abstract: In this paper, we present the results of multiple correlations between reliability (infant mortality and other reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with reliability defect density proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for reliability failures.

Abstract: This paper examines the impact of a thyristor controlled series capacitor (TCSC) on power system reliability. In this application, the TCSC is employed to adjust the natural power sharing of two different parallel transmission lines and, therefore, enable the maximum transmission capacity to be utilized. In this context, a reliability model of a multi-module TCSC has been developed and incorporated in the transmission system. The results of the investigations show a significant improvement system reliability when utilizing the improvement is measured using the two indices of loss of load expectation (LOLE) and loss of energy expectation (LOEE).

Abstract: This paper provides an account of the measures and procedures that contribute to the effective application of power system stabilizers. These include choice of input signals and methods of deriving them, control design procedures, coordination with other control and protective functions, hardware considerations to ensure functional reliability, and commissioning procedures.

Abstract: An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller performing virtual timing, formatting, and pattern generation for testing said devices; and a test head controlled by the controller, comprising pin electronics, dc subsystem, and support for self-testing built into the circuit. The computerized tester controller comprises pattern sequence control, pattern memory, scan memory, timing system and driver signal formatter, thereby executing virtually high speed functional tests based on test patterns, combined with ac parametric tests of said devices. Furthermore, the computerized tester controller dynamically transforms data stored in the computer into instructions for the test head and into pattern sequence matched to the digital function stimulus and response required by the design of the devices.

Abstract: A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising first, electrically testing the devices outside their specified operating voltage range, yet within the capabilities of the structures produced by the process steps, thereby generating raw electrical test data; second, comparing the test data to values expected from the design of the devices, thereby providing non-electrical characterization of the devices to verify compositional and structural features; and third, correlating the features with the documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices. After eliminating the outlier devices, the accepted devices do no longer have to undergo the traditional burn-in process.

Abstract: As the design of Micro-Electro-Mechanical Systems (MEMS) devices matures and their application extends to critical areas, the issues of reliability and long-term survivability become increasingly important. This paper reviews some general approaches to addressing the reliability and qualification of MEMS devices for space applications. The failure modes associated with different types of MEMS devices that are likely to occur, not only under normal terrestrial operations, but also those that are encountered in the harsh environments of space, will be identified.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Abstract: PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device equipped with a function for evaluation the reliability of data read out of a memory device in a non-volatile memory. SOLUTION: A switching control circuit 9 switches memory areas 1 and 2 into high-reliability mode and stores the same data in the memory areas 1 and 2, a comparator circuit 6 compares data read out of each of the memory areas 1 and 2 and when both the data are matched, the data are outputted to the outside.

Abstract: A variety of package parameters impact package reliability One of the parameters that does not get much attention is the variations in package design that are assembly and vendor related It was shown in this study that the solder pad size plays a big role in solder joint reliability The difference in solder pad size due to different vendors and processes can affect the reliability considerably In certain cases, the pad size effect can be so significant that it will override the effect of substrate thickness Our work indicates that in order to obtain good correlations between predictive engineering results and reliability tests data, this factor should not be ignored In this paper, finite element analysis was used to study the impact of substrate thickness on solder reliability for flip-chip PBGA (plastic ball grid array) packages The simulation results were experimentally validated with moire interferometry Both numerical and experimental results indicated that better solder reliability could be achieved by using thicker substrate However, the size of BGA solder pad was found to be crucial to BGA life In order to achieve higher C5 (controlled collapse chip carrier connection) reliability, a larger solder pad is preferred

Abstract: Polymer coatings are applied to chips and passive components to provide stress relief between the device/component and the plastic package and/or to provide mechanical and environmental protection. The semiconductor industry is actively pursuing a one mask, photosensitive dielectric process for stress-buffer and secondary passivation of memory die. A one mask photo-benzocyclobutene (BCB) process is compared to traditional two mask wet etch processes. This new one mask process reveals 1/3 the total wafer processing time and equivalent reliability (traditional MIL 883C testing) for passivated 100 lead static random access memory components (SRAMs). Reliability data are also presented for GaAs chips, and NiCr and TaN resistors which have been passivated by BCB.

Abstract: As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development activity is underway, implementing next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to assess process yield, process defects, and the reliability of no-flow underfill materials. Critical process design models are presented to predict chip motion during and after the chip placement process, enabling design of the placement process and underfill volume/mass to ensure high yields. Also reported are the results of reliability testing based on air to air and liquid to liquid thermal cycling.

Abstract: A fracture mechanics-based model has been developed for the reliability of wirebonds in IGBT-based power modules. Initial correlation of the model has been achieved based upon measurements of extremely localized displacements and temperature distributions of wirebonds and devices during both transient and steady states. The measurements have been performed by high-resolution holographic interferometry and high-speed infrared microscopy. The wirebond geometry has been found to have a profound effect on the localized temperature distribution and hence reliability.

Abstract: This chapter overviews the basic physical effects involved in programming and erasing of Flash memory cells, to provide the background for a deeper understanding of their operation and reliability. In particular, tunneling and high field transport are treated and the associated phenomena in MOS-FETs and Flash cells are described by means of measurements and simulations. Device degradation induced by charge injection into thin silicon dioxide layers is also briefly discussed.

Abstract: According to this invention, there is provided a drive apparatus for a power device having high- and low-voltage main electrodes and a control electrode, including a circuit for decreasing a voltage of the control electrode to a voltage of the control electrode which is not higher than a threshold voltage of the power device before a voltage between the high- and low-voltage main electrodes enters an overshoot region in a case where the power device is to be turned off. Therefore, electron injection can be stopped before the voltage between the main electrodes rises, the stability of the current density can be improved, and current concentration, oscillation, and the like can be prevented to improve reliability.