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  4. 1997
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  3. Reliability (semiconductor)
  4. 1997
Showing papers on "Reliability (semiconductor) published in 1997"
Journal Article•10.1093/oso/9780195090116.001.0001•
Hydrogen Bonding

[...]

Steve Scheiner
4 Sep 1997
TL;DR: The hydrogen bond is extensively studied using quantum chemical computations, which have yielded valuable insights into its fundamental nature. Such methods enable probing subtle electronic structure and examining inaccessible potential energy surface regions. The book explores the power of quantum chemistry in analyzing the hydrogen bond phenomenon and provides a systematic account of findings from decades of calculations.
Abstract: Abstract Because of the importance of the hydrogen bond, there have been scores of insights gained about its fundamental nature by quantum chemical computations over the years. Such methods can probe subtle characteristics of the electronic structure and examine regions of the potential energy surface that are simply not accessible by experimental means. The maturation of the techniques, codes, and computer hardware have permitted calculations of unprecedented reliability and rivaling the accuracy of experimental data. This book strives first toward an appreciation of the power of quantum chemistry to analyse the deepest roots of the hydrogen bond phenomenon. It offers a systematic and understandable account of decades of such calculations, focusing on the most important findings. This book provides readers with the tools to understand the original literature, and to perhaps carry out some calculations of their very own on systems of interest.

1,142 citations

Proceedings Article•10.1109/PEDS.1997.618742•
Fast power cycling test of IGBT modules in traction application

[...]

M. Held, P. Jacob1, G. Nicoletti1, P. Scacco1, M.-H. Poech •
École Polytechnique Fédérale de Lausanne1
26 May 1997
TL;DR: In this paper, a fast power cycling test method activating the main failure mechanism has been developed which allows reproduction of millions of temperature changes in a short time, and the applicability of fast testing is supported by a mechanical analysis.
Abstract: The numerous advantages of insulated gate bipolar transistor (IGBT) power modules and their ongoing development for higher voltage and current ratings make them interesting for traction applications. These applications imply high reliability requirements. One important requirement is the ability to withstand power cycles. Power cycles cause temperature changes which lead to a mechanical stress that can result in a failure. Lifting of bond wires is thereby the predominant failure mechanism. A fast power cycling test method activating the main failure mechanism has been developed which allows reproduction of millions of temperature changes in a short time. The applicability of fast testing is supported by a mechanical analysis. Test results show the number of cycles to failure as a function of temperature changes for an IGBT single switch. A descriptive model is deduced from the results.

591 citations

Proceedings Article•10.1109/IEDM.1997.650495•
A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization

[...]

Suresh Venkatesan1, A.V. Gelatos, B. Smith, R. Islam, J. Cope, B. Wilson, D. Tuttle, R. Cardwell, S. Anderson, M. Angyal, R. Bajaj, C. Capasso, P. Crabtree, Saroj Das, J. Farkas, Stanley M. Filipiak, B. Fiordalice, Melissa Freeman, Percy V. Gilbert, M. Herrick, Ajay Jain, H. Kawasaki, Charles Fredrick King, Jeffrey L. Klein, T. Lii, Kimberly G. Reid, T. Saaranen, Cindy Reidsema Simpson, T. Sparks, Paul G. Y. Tsui, R. Venkatraman, David K. Watts, E.J. Weitzman, R. Woodruff, I. Yang, Navakanta Bhat, Gregory Norman Hamilton, Y. Yu •
Motorola1
7 Dec 1997
TL;DR: In this paper, a high performance 020 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects, optimized for 18 V operation to provide high performance with low power-delay products and excellent reliability.
Abstract: A high performance 020 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects 015 /spl mu/m transistors (L/sub gate/=015/spl plusmn/004 /spl mu/m) are optimized for 18 V operation to provide high performance with low power-delay products and excellent reliability Copper has been integrated into the back-end to provide low resistance interconnects Critical layer pitches for the technology are summarized and enable fabrication of 76 /spl mu/m/sup 2/ 6T SRAM cells

191 citations

Book•
Influence of Temperature on Microelectronics and System Reliability: A Physics of Failure Approach

[...]

Pradeep Lall, Michael Pecht, Edward B. Hakim
30 Jun 1997
TL;DR: In this article, the authors present microelectronic device failure mechanisms in terms of their dependence on steady state temperature, temperature cycle, temperature gradient, and rate of change of temperature at the chip and package level.
Abstract: This book raises the level of understanding of thermal design criteria It provides the design team with sufficient knowledge to help them evaluate device architecture trade-offs and the effects of operating temperatures The author provides readers a sound scientific basis for system operation at realistic steady state temperatures without reliability penalties Higher temperature performance than is commonly recommended is shown to be cost effective in production for life cycle costsThe microelectronic package considered in the book is assumed to consist of a semiconductor device with first-level interconnects that may be wirebonds, flip-chip, or tape automated bonds; die attach; substrate; substrate attach; case; lid; lid seal; and lead seal The temperature effects on electrical parameters of both bipolar and MOSFET devices are discussed, and models quantifying the temperature effects on package elements are identified Temperature-related models have been used to derive derating criteria for determining the maximum and minimum allowable temperature stresses for a given microelectronic package architectureThe first chapter outlines problems with some of the current modeling strategies The next two chapters present microelectronic device failure mechanisms in terms of their dependence on steady state temperature, temperature cycle, temperature gradient, and rate of change of temperature at the chip and package level Physics-of-failure based models used to characterize these failure mechanisms are identified and the variabilities in temperature dependence of each of the failure mechanisms are characterized Chapters 4 and 5 describe the effects of temperature on the performance characteristics of MOS and bipolar devices Chapter 6 discusses using high-temperature stress screens, including burn-in, for high-reliability applications The burn-in conditions used by some manufacturers are examined and a physics-of-failure approach is described The

141 citations

Journal Article•10.1109/43.644613•
iTEM: a temperature-dependent electromigration reliability diagnosis tool

[...]

Chin-Chi Teng, Yi-Kan Cheng1, Elyse Rosenbaum2, Sung-Mo Kang3•
Synopsys1, IBM2, University of Illinois at Urbana–Champaign3
01 Dec 1997-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TL;DR: By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis, and it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation.
Abstract: In this paper, we present a new electromigration reliability diagnosis tool (iTEM) for CMOS VLSI circuits. Unlike previous electromigration reliability tools, iTEM can estimate the interconnect temperature rise due to joule heating and heat conduction from the substrate using a newly developed lumped thermal model. By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis. Moreover, it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation.

100 citations

Proceedings Article•10.1109/IAS.1997.630841•
Power cycling reliability of IGBT power modules

[...]

V.A. Sankaran1, C. Chen, C.S. Avant, X. Xu•
Ford Motor Company1
5 Oct 1997
TL;DR: In this article, the power cycling reliability of IGBT power dice is investigated. But, the reliability of the dice is not evaluated and the results from the tests are summarized in this paper.
Abstract: The goal of this study was to understand the power cycling reliability of IGBT power modules. These power modules are made up of multi-layer stacks and consist of multiple power dice in parallel. The interconnection schemes within the module include leadframes soldered to substrate, die attachment using solder and wirebonds. Thermal and power cycling fatigues material interfaces because of the CTE mismatch between dissimilar materials. In addition, wirebonds on the dice are prone to debonding because of the thermally induced stresses. Tests were designed to understand the power cycling reliability of these large transistor modules. Results from the tests are summarized in this paper.

71 citations

Proceedings Article•10.1109/ISPSD.1997.601422•
Pressure contact assembly technology of high power devices

[...]

Hideo Matsuda1, M. Hiyoshi1, N. Kawamura1•
Toshiba1
26 May 1997
TL;DR: In this article, pressure contact technology applied to high power semiconductor devices is described, and specific application to multiple chip assembly, particularly IGBT chips, is dealt with, and improved reliability characteristics are demonstrated.
Abstract: The paper describes pressure contact technology applied to high power semiconductor devices. Specific application to multiple chip assembly, particularly IGBT chips, is dealt with, and improved reliability characteristics are demonstrated.

41 citations

Journal Article•10.1017/S0269888997003020•
Combining functional and structural reasoning for safety analysis of electrical designs

[...]

Chris Price1, Neal Snooke1, D. R. Pugh1, John Hunt1, M. S. Wilson1 •
Aberystwyth University1
01 Sep 1997-Knowledge Engineering Review
TL;DR: This paper describes how the intended functions of a circuit design can be combined with a qualitative model of the electrical circuit that fulfils the functions, and used to analyse the safety of the design.
Abstract: Increasing complexity of design in automotive electrical systems has been paralleled by increased demands for analysis of the safety and reliability aspects of those designs. Such demands can place a great burden on the engineers charged with carrying out the analysis. This paper describes how the intended functions of a circuit design can be combined with a qualitative model of the electrical circuit that fulfils the functions, and used to analyse the safety of the design. FLAME, an automated failure mode and effects analysis system based on these techniques, is described in detail. FLAME has been developed over several years, and is capable of composing an FMEA report for many different electrical subsystems. The paper also addresses the issue of how the use of functional and structural reasoning can be extended to sneak circuit analysis and fault tree analysis.

32 citations

Patent•
Battery and its manufacture

[...]

Shigeru Aihara, Atsushi Arakane, Junichi Hosokawa, Hideo Ichimura, Kenji Kawaguchi, Makiko Kichise, Hironori Kuriki, Masaharu Moriyasu, Shinji Nakadeguchi, Takashi Nishimura, Hirochika Ozaki, Hisashi Shioda, Daigo Takemura, Hiroaki Urushibata, Seiji Yoshioka, 真治 中出口, 省二 吉岡, 万希子 吉瀬, 久 塩田, 博規 尾崎, 憲治 川口, 英男 市村, 宏徳 栗木, 雅治 森安, 広明 漆畑, 茂 相原, 大吾 竹村, 純一 細川, 淳 荒金, 隆 西村 
26 May 1997
TL;DR: In this paper, a battery body is contained in a battery case composed by a laminate material comprising a metallic foil and its armor materials with an electrode terminal 3 projected from an end part of the case.
Abstract: PROBLEM TO BE SOLVED: To provide a battery having a battery case having improved energy density, improved insulating characteristic, no seal leaks and high reliability and its manufacturing method. SOLUTION: In this battery, a battery body 7 is contained in a battery case 1 composed by a laminate material comprising a metallic foil 5 and its armor materials 6a, 6b with an electrode terminal 3 projected from an end part of the case 1. Sealing material 4 to be weld with the armor material 6a and the terminal 3 is intervened between a sealing part 2 of the case 1 in which the terminal 3 is projected therefrom to seal the case 1 by heat-welding. An insulating film 9 thicker than the sealing material 4 is arranged at the end part of the case 1 in which the terminal 3 is projected therefrom. COPYRIGHT: (C)2000,JPO

31 citations

Preprint•10.48550/arxiv.quant-ph/9703013•
On Reliability Function of Quantum Communication Channel

[...]

M. V. Burnashev, A. S. Holevo
1 Jan 1997
TL;DR: The reliability function bounds for quantum pure state channels are derived, providing an alternative proof of the coding theorem.
Abstract: The reliability function gives the rate of exponential convergence to zero of the error probability in a communication channel. In this paper bounds for the reliability function of a quantum pure state channel are given, reminiscent of the corresponding classical bounds. This in particular suggests an alternative proof of the coding theorem for quantum noiseless channel, which would make no use of the notion of typical subspace. Example of binary quantum channel is considered in some detail.

30 citations

Journal Article•10.2460/javma.1997.211.09.1142•
Reliability of early radiographic evaluations for canine hip dysplasia obtained from the standard ventrodorsal radiographic projection

[...]

Elizabeth A. Corley, G. G. Keller, Jimmy C. Lattimer, Mark R. Ellersieck
01 Nov 1997-Javma-journal of The American Veterinary Medical Association
TL;DR: Preliminary evaluations of hip joint status in dogs are generally reliable, but dogs that receive a preliminary evaluation of fair phenotype or mild CHD should be reevaluated after 24 months of age.
Abstract: Objective To determine reliability of preliminary evaluations for canine hip dysplasia (CHD) performed by the Orthopedic Foundation for Animals on dogs between 3 and 18 months of age. Design Retrospective analysis of data from the Orthopedic Foundation for Animals database. Animals 2,332 Golden Retrievers, Labrador Retrievers, German Shepherd Dogs, and Rottweilers for which preliminary evaluation had been performed between 3 and 18 months of age and for which results of a definitive evaluation performed after 24 months of age were available. Procedure Each radiograph was evaluated, and hip joint status was graded as excellent, good, fair, or borderline phenotype or mild, moderate, or severe dysplasia. Preliminary evaluations were performed by 1 radiologist; definitive evaluations were the consensus of 3 radiologists. Reliability of preliminary evaluations was calculated as the percentage of definitive evaluations (normal vs dysplastic) that were unchanged from preliminary evaluations. Results Reliability of a preliminary evaluation of normal hip joint phenotype decreased significantly as the preliminary evaluation changed from excellent (100%) to good (97.9%) to fair (76.9%) phenotype. Reliability of a preliminary evaluation of CHD increased significantly as the preliminary evaluation changed from mild (84.4%) to moderate (97.4%) CHD. Reliability of preliminary evaluations increased significantly as age at the time of preliminary evaluation increased, regardless of whether dogs received a preliminary evaluation of normal phenotype or CHD. Clinical Implications Results suggest that preliminary evaluations of hip joint status in dogs are generally reliable. However, dogs that receive a preliminary evaluation of fair phenotype or mild CHD should be reevaluated after 24 months of age. ( J Am Vet Med Assoc 1997;211:1142–1146)
Proceedings Article•10.1109/IEMDC.1997.604066•
On-line current monitoring to diagnose airgap eccentricity-an industrial case history of a large high-voltage three-phase induction motor

[...]

W.T. Thomson1, D. Rankin, David G. Dorrell2•
Robert Gordon University1, University of Reading2
18 May 1997
TL;DR: In this paper, an appraisal of online monitoring techniques to detect airgap eccentricity in three-phase induction motors is presented, and results from an industrial case history show that an improved interpretation of the current spectrum can increase the reliability of diagnosing air gap eccentricity.
Abstract: An appraisal of online monitoring techniques to detect airgap eccentricity in three-phase induction motors is presented. Results from an industrial case history show that an improved interpretation of the current spectrum can increase the reliability of diagnosing airgap eccentricity in large HV three-phase induction motors.
Proceedings Article•10.1109/PCCON.1997.645620•
Line voltage sensorless three phase PWM converter by tracking control of operating frequency

[...]

Tokuo Ohnishi1, K. Fujii•
University of Tokushima1
3 Aug 1997
TL;DR: This paper proposes a novel control strategy of the three phase PWM converter by tracking control of the operating frequency based on the power balance of the converter.
Abstract: Much research about a power line voltage sensorless PWM converter has been presented from the view points of the simplicity and the reliability of the control system. Most schemes need some calculations to estimate the power line voltage using circuit parameters. In this paper, we propose a novel control strategy of the three phase PWM converter by tracking control of the operating frequency based on the power balance of the converter. The system is composed of the direct PWM control loop of the instantaneous active and reactive current. The features of the proposed PWM control system are simplicity without sensing the line voltage, high reliability with poor dependence of the circuit parameters, high efficiency and fast response etc.
Journal Article•10.1557/PROC-483-369•
Material Requirements for High Voltage, High Power IGBT Devices

[...]

R. Zehringer, A. Stuck, T. Lang
01 Jan 1997-MRS Proceedings
TL;DR: The two basic package types of current IGBT modules, which evolved from opposing requirements of traction and power transmission applications, are presented in this paper, where it is shown that reliability and lifetime aspects given by traction puts most stringent limitations on the choice of materials at given cost targets.
Abstract: The two basic package types of current IGBT modules, which evolved from opposing requirements of traction and power transmission applications, are presented. It is shown that reliability and lifetime aspects given by traction puts most stringent limitations on the choice of materials at given cost targets. The materials used today for high power packaging and the future developments of high power IGBT-packages are discussed.
Patent•
Electronic device having an acceleration-sensitive sensor

[...]

Bernhard Mattes1, Lothar Gademann1, Werner Nitschke1, Dietrich Dipl Ing Dr Bergfried1, Gerald Hopf1, Botho Ziegenbein1, Klaus Meder1, Ralf Henne1, Thomas Walker1, Bernd Maihoefer1, Frank Kursawe1, Peter Schaedler1 •
Bosch1
16 Oct 1997
TL;DR: In this paper, an electronic device includes a resonant circuit and an evaluation circuit, which is coupled to the resonant circuits to determine a performance reliability of the acceleration sensitive sensor.
Abstract: An electronic device includes a resonant circuit and an evaluation circuit. The resonant circuit includes an acceleration-sensitive sensor which is excited to vibrate during a testing phase of the acceleration-sensitive sensor. The evaluation circuit is coupled to the resonant circuit to determine a performance reliability of the acceleration-sensitive sensor.
Journal Article•
Integration of ferroelectric nonvolatile memories

[...]

R. E. Jones
01 Jan 1997-Solid State Technology
Patent•
Cooling device and cooling method

[...]

Takahashi Masahiko, Otani Yasumi, Toru Kuriyama, Hideki Nakagome, Roohana Chiyandora Teiraka, Hatakeyama Hideo 
2 Dec 1997
TL;DR: In this paper, the authors proposed a method for the enhancement of the freedom of installation of a cooling device, the freedom and reliability of the device by a method wherein when a material to be cooled is cooled by a cooling source, the cooling source and the material to being cooled are thermally connected to each other and when the material is heat-insulated, the material and the cooling sources are thermically separated from each other.
Abstract: PROBLEM TO BE SOLVED: To contrive the enhancement of the freedom of installation of a cooling device, the freedom of use of the device, the stability of the device and the reliability of the device by a method wherein when a material to be cooled is cooled by a cooling source, the cooling source and the material to be cooled are thermally connected to each other and when the material to be cooled is heat-insulated, the cooling source and the material to be cooled are thermally separated from each other SOLUTION: A coil part 41 is provided with a vacuum container 43, a superconducting coil 44 housed in this container 43 and a thermal shield 45 arranged between the coil 44 and the container 43 in such a way as to surround the coil 44, while a refrigeration part 42 is constituted of a vacuum container 60 and an air cooling refrigerator 61 arranged in this container 60 Both of the coil part 41 and the part 42 are made to couple each other (are made to connect thermally each other) without breaking a vacuum only at the time when the coil 44 is cooled When the coil 44 is heat-insulated, the coil part 41 and the part 42 are made to separate each other (are made to separate thermally each other)
Proceedings Article•10.1109/BIPOL.1997.647433•
High reliability metal insulator metal capacitors for silicon germanium analog applications

[...]

Kenneth J. Stein1, J. Kocis, G. Hueckel, E. Eld, T. Bartush, Robert A. Groves, N. Greco, David Harame, T. Tewksbury •
IBM1
28 Sep 1997
TL;DR: In this article, a planar metal-insulator-metal capacitor (MIMCAP) process is introduced, integrated in a Silicon Germanium (SiGe) HBT process, which has excellent yield, reliability and repeatability.
Abstract: In this work, a novel "planar" metal-insulator-metal capacitor (MIMCAP) process is introduced, integrated in a Silicon Germanium (SiGe) HBT process, which has excellent yield, reliability and repeatability. The MIMCAP was characterized for DC and AC parametrics, and stressed at elevated biases and temperatures to assess reliability. An equivalent circuit and SPICE model were generated, and good agreement was found between the simulated and measured characteristics. A MIMCAP with high device/bottom plate capacitance ratio, excellent yield and reliability are critical needs in high quality passives for the fabrication of advanced analog mixed/signal circuits with on-chip components. In collaboration with Analog Devices, SiGe HBT voltage controlled oscillators (VCO) circuits were designed with both MIMCAP and substrate capacitor controls to demonstrate the leverage of this novel passive element.
Patent•
Wafer burn-in test circuit for a semiconductor memory device

[...]

Yun-Sang Lee1•
Samsung1
23 Dec 1997
TL;DR: In this paper, the authors proposed a wafer burn-in test circuit for improving the reliability of a semiconductor memory device by performing a level transition on the signals that drive the sub-word line drivers.
Abstract: A semiconductor memory device has independently controllable word lines, thereby allowing various background data patterns to be freely written to the memory cells to perform various wafer burn-in tests. This allows the leakage between adjacent memory cells to be efficiently tested by independently controllable word line activation signals, as well as the reliability of bit lines. A wafer burn-in test circuit for performing this improved burn-in test improves the reliability of the device by performing a level transition on the signals that drive the sub word line drivers, thereby eliminating the need to apply a high voltage to one transistor in the sub word line driver.
Patent•
Test system and methodology to improve stacked NAND gate based critical path performance and reliability

[...]

Peng Fang1, Sunil N. Shabde1•
Advanced Micro Devices1
5 Sep 1997
TL;DR: A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data.
Abstract: A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.
Journal Article•10.1016/S0026-2714(97)00131-5•
Ga As power MMIC : A design methodology for reliability

[...]

J. L. Muraro1, F. Coppel2, G. Gregoris2, P.G. Tizien, J.L. Roux •
Hoffmann-La Roche1, Alcatel-Lucent2
01 Oct 1997-Microelectronics Reliability
TL;DR: In this article, the authors introduce a design methodology which defines a safe RF operating area for reliable Monolithic Microwave Power Amplifiers (MPMP) under temperature, DC and RF accelerating stress conditions.
Patent•
Semiconductor device and pattern including varying transistor patterns for evaluating characteristics

[...]

Makoto Hamada1, Ken Shono1•
Fujitsu1
4 Nov 1997
TL;DR: In this article, the authors provide a simulation method capable of efficiently evaluating reliability of gate oxide films formed on the elements within short periods of time to evaluate characteristics of a semiconductor device made up of elements of any size and any number.
Abstract: To provide a simulation method capable of efficiently evaluating reliability of gate oxide films formed on the elements within short periods of time to evaluate characteristics of a semiconductor device made up of elements of any size and any number. In a semiconductor device having transistors formed thereon, a pattern 1 for evaluating characteristics of a semiconductor device characterized in that gate area portions 9, gate bird's-beak portions 10 and LOCOS bird's-beak portions 11, are factors affecting the insulation breakdown of the gate oxide film, are rendered to be variable, so that the shapes of these portions can be handled as independent parameters.
Journal Article•10.1109/2943.589894•
Pressure sensor performance and reliability

[...]

T. Maudie1, J. Wertz•
Motorola1
01 May 1997-IEEE Industry Applications Magazine
TL;DR: The development of epoxy packaging capability for silicon sensors, improved die bonding material, and reliability testing results indicate that the silicon piezo-resistive transducer (PRT) promises to be the next plateau.
Abstract: Pressure sensor devices are used to monitor the performance characteristics of various systems within the appliance industry. The household washing machine has long employed sensor devices to monitor and control the tub water level during fill cycles. These devices have evolved from early watertight or float switches to rubber diaphragm mechanical-type devices. The development of epoxy packaging capability for silicon sensors, improved die bonding material, and reliability testing results indicate that the silicon piezo-resistive transducer (PRT) promises to be the next plateau. Silicon PRT electronic devices offer a significant size and weight reduction over these mechanical devices. The authors discuss the reliability testing considerations for the sensors and reliability testing for the appliance industry.
Proceedings Article•10.1109/VLSIT.1997.623717•
Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology

[...]

Bin Yu, Dong-Hyuk Ju1, Tsu-Jae King1, Chenming Hu2•
University of California, Berkeley1, Hodges University2
10 Jun 1997
Journal Article•10.1109/61.636928•
Secular change in characteristics of thyristors used in HVDC valve

[...]

M. Sampei, T. Yamada, S. Tanabe1, H. Takeda1, S. Kobayashi1 •
Toshiba1
01 Jul 1997-IEEE Transactions on Power Delivery
TL;DR: In this article, the authors examined changes in the characteristics of the thyristors and estimated their life-time in the Kamikita-Honshu HVDC link, and verified that the older thyristor had the characteristics and service life equivalent to those of the new ones.
Abstract: The Hokkaido-Honshu HVDC link entered service in 1979 for the first phase (150 MW, 125 kV-1200 A) and in 1980 for the second phase (300 MW, 250 kV-1200 A) and has since been operating in good condition. In the Kamikita converter station situated on the Honshu side, the thyristor valves for the first and second phases use 1344 thyristors rated 4 kV-1.5 kA. To examine secular changes in the characteristics of thyristors and estimate their life expectancy, we picked up eight thyristors from the thyristor valves, measured the main characteristics and compared measurements with the corresponding values measured before they entered service. Further, two thyristors were subjected to temperature and voltage acceleration tests to check for a change over time of leakage current. From the results of these investigations it was verified that the thyristors that have been in service for 16 years have the characteristics and service life equivalent to those of the new ones. But further investigation is required as to the change of turn-off characteristics.
Journal Article•10.1109/16.622593•
Simulating process-induced gate oxide damage in circuits

[...]

R. Tu1, J.C. King2, Hyungcheol Shin, Chenming Hu3•
Advanced Micro Devices1, Rockwell International2, University of California, Berkeley3
01 Sep 1997-IEEE Transactions on Electron Devices
TL;DR: In this paper, the authors present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability.
Abstract: Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator.
Patent•
Semiconductor device and manufacture thereof

[...]

Fujishiro Hironori, Nagai Kiyoshi
15 Aug 1997
TL;DR: In this article, a polyimide film 17 is partially provided as a dielectric film onto a microstrip line 7 and an open stub 8 in an input impedance-matching circuit 5 and an output impedance matching circuit 6 both formed on a polyamide board 16.
Abstract: PROBLEM TO BE SOLVED: To enable a semiconductor device to be easily adjusted and enhanced in reliability after it is assembled. SOLUTION: A polyimide film 17 is partially provided as a dielectric film onto a microstrip line 7 and an open stub 8 in an input impedance-matching circuit 5 and an output impedance-matching circuit 6 both formed on a dielectric board 16. The polyimide film 17 is formed through such a manner that a proper amount of liquid polyimide is dropped down and cured at a temperature of 300 deg.C or so.
Proceedings Article•10.1109/SOI.1997.634937•
A manufacturable SOI CMOS process for low power digital, analog, and RF applications

[...]

M. Stuber, P. Dennies, G. Lyons, T. Kobayashi, H. Domyo 
6 Oct 1997
TL;DR: Peregrine Semiconductor's UTSi(R) technology is a silicon-on-sapphire (SOS) CMOS process with proven manufacturability for high-performance, low-power commercial CMOS applications as discussed by the authors.
Abstract: Peregrine Semiconductor's UTSi(R) technology is a silicon-on-sapphire (SOS) CMOS process with proven manufacturability for high-performance, low-power commercial CMOS applications. Data are presented from the 0.7/spl mu/m single poly, triple metal process currently in production. The UTSi(R) CMOS process is compatible with standard CMOS processing equipment and techniques. Process parameters show excellent control and the process has demonstrated high reliability. Transistor and device parametric performance show this process to be capable of manufacturing low power products for digital, RF, and analog applications. The technology is fully qualified in plastic packages and is ready for high volume, low cost production. The process is shown to be scaleable to at least 0.5/spl mu/m for further performance gains.
Proceedings Article•10.1109/VTSA.1997.614718•
Copper Interconnect: Fabrication And Reliability

[...]

C.-K. Hu, J.M.E. Harper
3 Jun 1997
TL;DR: The materials, processes, and reliability issues in the development of multi-level Cdpolyimide chip interconnections are described in this article, where prototype four-level cdpolyamide structures have been fabricated by using a damascene process which maintains planarity at each level.
Abstract: The materials, processes, and reliability issues in the development of multi-level Cu chip interconnections are described. Prototype four-level Cdpolyimide structures have been fabricated by using a damascene process which maintains planarity at each level. Electromigration lifetime for two-level Cu interconnections is found to be longer than that of Al(Cu) whle having approximately twice the conductivity.
Proceedings Article•10.1109/ICMEL.1997.632933•
Reliability testing of power VDMOS transistors

[...]

N. Tosic, B. Pesic, Ninoslav Stojadinovic
14 Sep 1997
TL;DR: It has been found that electromigration at the source/drain contacts, intermetallic processes at the solder joint and gate oxide breakdown are the major failure mechanisms limiting the reliability of investigated devices.
Abstract: In this paper, a summary of results of reliability investigation of power VDMOS transistors is given. The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated degradation processes and failure mechanisms in power VDMOSFETs subjected to HTRB (High-Temperature-Reverse-Bias) testing at three different temperatures (150/spl deg/C, 125/spl deg/C and 100/spl deg/C). The instabilities of the electrical DC parameters and catastrophical failures are observed and analyzed. It has been found that electromigration at the source/drain contacts, intermetallic processes at the solder joint and gate oxide breakdown are the major failure mechanisms limiting the reliability of investigated devices.
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