Abstract: IGBT power semiconductor modules have become of the utmost importance for traction applications. Their control circuitry is of much lower expenditure than those for GTOs. Power converters for tramways, elevators and railway locomotives will be equipped with IGBT modules in the future. However, the reliability of these power modules is still a serious concern, compared to the comparable good reliability of GTO presspack technology. Although first approaches have already been announced, the presspacking of IGBTs is a rather difficult and expensive process, because of the complex IGBT structure and the wafer processing yields in IGBT wafer manufacturing. On the other hand, tough operation conditions in case of traction applications cause reliability requirements which need significant improvements of the present conventional wire bond/die-attach module packaging technology. Reliability tests, which should represent traction operation of modules in the field, show that wire bonding and soldering may cause failures of the modules. The paper presents analysis results and ways of how these problems might be solved.

Abstract: Introduction Materials Construction schemes and strategies Membrane switch Printed circuits Printed components Resistors Manufacturing Assembly General design guidelines Testing performance and reliability Applications and case histories PTF advantages and limitations The economics of PTF The future of PTF PTF and the environment Glossary and Appendix

Abstract: The pervasiveness of automotive passive restraint systems has emphasized the need for improving system reliability while simultaneously reducing the cost and size of the system. This paper describes an accelerometer that utilizes silicon micromachining in a dissolved wafer process and a CMOS ASIC along with low cost plastic packaging to support the requirements of the next generation of automotive passive restraint systems.

Abstract: Statistical Electromigration Budgeting (SEB) is a novel method for setting and verifying electromigration (EM) design requirements for VLSI interconnect. SEB exploits the statistical nature of EM reliability to selectively supersede fixed current density design rules for some interconnect, allowing increased chip performance while simultaneously quantifying chip-level EM reliability to directly assure design conformance to reliability requirements. The concept and method of SEB are introduced, and some results from its application in the design and verification of the Alpha 21164300 microprocessor are given.

Abstract: MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD/EOS reliability through nMOSFET drain design for a 0.35 /spl mu/m CMOS process that compromises neither the performance nor the hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option for the I/O transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and its implementation cost was lower than a silicide-block option. The paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot-carrier data are reviewed.

Abstract: A new wafer-level measurement technique, the differential gate antenna analysis, has been developed to detect weaknesses in sub-micrometer oxide. This simple technique involves the use of dual antenna structures with different gate oxide areas but the same antenna area ratio. The critical parameter is the difference in their failure levels. It is shown that such a differential measurement of antenna failures correlates with product failure during accelerated life testing. The differential antenna structures are thus proven useful for real-time wafer-level monitoring of oxide reliability.

Abstract: Unrestricted freedom, reliability and speed of communications is essential to satisfactory international organization, especially in time of emergency.

Abstract: An approach to the security evaluation of a composite power system is proposed which uses probability techniques for quantitative power system reliability analysis. This approach incorporates both steady-state and transient-state considerations in the reliability evaluation of composite power systems.

Abstract: The performance and reliability of a low-cost three-dimensional plastic moulded vertical multi-chip module concept is presented. Performance was evaluated using custom designed chips incorporating thermal, thermomechanical, electrical and reliability test structures. Results of performance are presented and are shown to correlate well with thermal, thermomechanical and electrical simulations. The thermal and thermomechanical performances are sufficient to allow use of the MCM-V technique in a wide range of applications without the need for special cooling techniques. Reliability testing to space level standards was carried out on 53 technology demonstrator modules incorporating the test chips and a high level of reliability has been demonstrated.

Abstract: Designing reliable CMOS chips involves careful circuit design, with attention directed to some of the potential reliability problems such as electromigration and hot-carrier effects. This paper considers logic synthesis to optimize, early in the design phase, against electromigration and hot-carrier degradation. The electromigration and hot-carrier effects are estimated at the gate level using signal activity measure (average number of transitions at circuit nodes). Results on MCNC synthesis benchmarks show that logic can be synthesized to optimize for higher reliability and lower silicon area. A minimum-area circuit is usually not associated with highest reliability. >

Abstract: PURPOSE:To expand a condition under which the protective function of an insulated-gate semiconductor device with a built-in protective circuit functions, to enhance the shutting-off of heating, to prevent a malfunction and to enhance ease-of-use features. CONSTITUTION:An insulated-gate semiconductor device is provided with a power insulated-gate semiconductor element (M9), with MOSFETs (M1 to M7), for a protective circuit, which control the power insulated-gate semiconductor element, with a constant-voltage circuit which utilizes the forward voltage of diodes (D2a to D2f) for the constant-voltage circuit and with diodes (D1, D0a to D0d), for voltage limitation, which control the upper limit of a power- supply voltage for the constant-voltage circuit. power of the diodes for current limitation is supplied from the external gate terminal of the power insulated-gate semiconductor element. Thereby, an effect that the reliability of the insulated- gate semiconductor device with the built-in protective circuit is enhanced and that ease-of-use features are enhanced is obtained.

Abstract: The motivation to develop high-temperature resistant smart-power products and the impact of silicon-on-insulator (SOI) technology are discussed. The electrical and thermal behaviour of devices on SOI-substrates is illustrated, with examples, showing that smart-power integrated circuits can be designed for operation at chip temperatures up to 200 °C allowing the use of low-cost packaging techniques at ambient temperatures up to 130 °C. Some reliability issues limiting a broader application of smart power devices at high temperature at the present time are also considered.

Abstract: With decreasing geometries of MOS transistors in VLSI devices, the influence of fluctuations of process parameters during manufacturing will become more and more important, because process tolerances are not proportionally scaled to geometries. These fluctuations result in a performance spread of the devices produced by a certain process. For instance the clock rate of a microprocessor as a typical performance indicator, can vary in a wide range. One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. In the following paper, an efficient method for accurate prediction of the performance spread of integrated circuits is discussed and demonstrated by simulations. All the simulations are verified by measurements on a test-circuit with a huge number of test devices. The method is applied to different signal distribution networks of wafer scale integration devices to show the sensitivity of performance to these variations. >

Abstract: The physics-of-failure testing approach for multichip modules presented in this paper determines test levels based on failure mechanisms, failure modes, and stresses for the application. It uses quantitative failure models and acceleration transforms and adapts the knowledge of dominant failure mechanisms to the selection of accelerating stress parameters. The stress levels, designed specifically for each test article, are based on manufacturing processes, geometry, and materials.

Abstract: We report on the reliability of an InP-based heterojunction bipolar transistor IC technology for very high-speed and low power applications. We have performed extensive accelerated lifetest experiments under bias and temperature stress and found mean-time-to-failures (MTTF) in excess of 10/sup 7/ hours at 125/spl deg/C junction temperatures. We have also exposed our devices to a hydrogen ambient, particularly important for integrated circuits in hermetically sealed packages. We did not observe any difference in the characteristics of devices with or without exposure to hydrogen ambient. In addition we have performed extensive lifetest experiments on tantalum-nitride (TaN) thin-film resistors (TFR) used in our IC process. Our TFR reliability performance exceeded the active device reliability, as required in a reliable IC process. >

Abstract: This paper compares metal matrix composite (MMC) baseplate power modules to standard copper baseplate power modules with respect to high current applications. The comparison is made both from a reliability and a package integration perspective. Reliability continues to be a key concern in applications where motor drives are subjected to thermal cycling. Modules with copper baseplates exhibit poor mechanical reliability since the thermal mismatches are high between the baseplate and the other materials in the package. Package integration of the power stage with the rest of the package is difficult with copper based modules since the only geometry that can be economically produced is stamped two dimensional baseplates. MMC materials are combinations of metals and ceramics with variable properties. A silicon carbide/aluminum composite (a moldable material with controlled thermal expansion coefficient) offers elegant solutions to the reliability and package integration concerns of standard modules. This study, conducted at Motorola's Hybrid Power Module Operation, examines the benefits that can be realized in both of these areas by using MMC baseplates in high current power modules. Measurement and finite element methods are used to study reliability. Additionally, design concepts for integrated packaging and integrated power systems are also explored.

Abstract: A Monte-Carlo reliability simulator for integrated circuits (IC) that incorporates the effects of process flaws, material properties, the mask layout, and use conditions is presented. The mask layout is decomposed into distinct objects, such as contiguous metal runs, vias, contacts, and gate-oxides, for which user-defined distributions are used for determining the failure probability. These distributions are represented by a mixture of defect-related and wearout-related distributions. The failure distributions for nets (sets of interconnected layout objects) are obtained by combining the distributions of their component objects. System reliability is obtained by applying control variate sampling to the logic network which is comprised of all nets. The effects of k-out-of-n substructures within the reliability network are accounted for. The methodology is illustrated by the effect of particulate-induced defects on metal runs and vias in a simple test circuit. The results qualitatively verify the methodology and show that predictions which incorporate failures due to process flaws are appreciably more pessimistic than those obtained from current practice.

Abstract: The design of portable devices certainly requires consideration of the peak power consumption for reliability and proper circuit operation, but more critical is the time averaged power consumption which is directly proportional to the battery weight and volume required to operate circuits for a given amount of time. In fact, the approaches which will be presented to minimize the average power consumption will also reduce the peak power consumption and improve reliability.

Abstract: Technical requirements for leadframe material with the trends in packaging technology such as shrink in size and increasing heat dissipation are first summarized. A new precipitation hardening leadframe copper alloy which meets technical requirements is then introduced in terms of advantages related with package reliability.

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor memory in which mounting reliability and power source/ground plane characteristics can be increased even when the number of terminals is large SOLUTION: Even when the size of a mounting substrate is large, the mounting reliability of a solder ball 9 can be increased Thus, a BGA type semiconductor device with the large number of pin terminals in 700-1000 pin classes or more can be realized As a result, it is not necessary to provide any socket for mounting necessary at the time of using a PGA type semiconductor device so that it is possible to reduce costs Moreover, when the number of pin terminals is large, terminals for a signal can be arranged like a full matrix with the high degree of freedom, and the size of a semiconductor chip 2 can be reduced The reliability of a bump 3 between the semiconductor chip 2 and a BGA substrate 1 can be increased, and the multi-pin semiconductor can be realized at low costs

Abstract: A process for fabricating MOSFET devices, in which performance, as well as reliability enhancements, are included, has been developed. An LDD process, using first an ion implanted phosphorous step, to address hot carrier lifetime phenomena, followed by a arsenic ion implantation step, used to improve device performance, is described.

Abstract: Gate antenna structures have been developed to detect charge induced process damage to sub-micron gate oxide. For the first time, this damage is correlated with product failure due to gate oxide in accelerated life testing. These antenna structures are thus proven to be useful for wafer level gate oxide reliability screening.

Abstract: In the past five years, a sufficient understanding of hot-carrier degradation has been obtained to slow reliability predictions of digital and analogue CMOS circuits. The proven quasi-static behaviour and a universal time dependence of the degradation, which is independent of the specific stress condition, prove helpful in developing simple formulae for predicting n-channel lifetimes in digital circuits. In p-channel devices, in contrast, a detailed quantitative understanding is obtained which leads to a precise description of the degradation in this type of device. Reliability predictions of digital CMOS circuits are performed on this basis. Analogue circuits operate with long-channel devices and in regimes differing from those for digital applications, thus requiring additional considerations. Channel-length dependences of the hot-carrier degradation have been found for a variety of electrical parameters relevant to the analogue operation of n- and p-MOSFETs. In particular, a new degradation effect independent of channel length that is important for modelling analogue circuits has been discovered in p-MOSFETs. The reliability of devices in analogue circuits is described and tested on this basis.

Abstract: A high voltage and a large current rating, 2000 V 500 A IGBT (Insulated Gate Bipolar Transistor) module with a newly developed structure was described. The module features a small size, high reliability and low electrical noise characteristics. The high reliability is realized by using a low thermal expansion base. The modules are suitable for applications to high speed switching levels with high blocking voltages such as in traction motor drives.

Abstract: A wafer level dielectric breakdown reliability measurement technique using logarithmically stepped-up stress current density is proposed, and the effectiveness of this technique is demonstrated. The stepped current time-dependent dielectric breakdown (SCTDDB) measurement starts at a very low stress current density (10 -5 A/cm 2 ), and it steps up logarithmically to a maximum stress current density (1.0 A/cm 2 ) until oxide breakdown occurs. The SCTDDB measurement has high detection sensitivity for defect-related breakdown, a wide dynamic range (10 -5 to 10 2 C/cm 2 ), adequate measurement time (within 60 s/chip), and data compatibility with conventional constant current TDDB result. The SCT-DDB technique is a very simple and powerful evaluation tool for thin silicon dioxide reliability analysis