Abstract: A security system having a two way wireless keypad which operates in a particular manner for improved operation. The keypad processes information to effectively reduce communications between the control panel and the keypad. The keypad selectively activates and deactivates a transmitter and receiver arrangement for power conservation reasons. The system provides confirmation of communications between the keypad and the control panel to increase the reliability of the system.

Abstract: Abstract This is a practical text for those who wish to analyse data from Reliability studies. The emphasis is on clear explanation of the techniques used, supported by extensive mathematical and statistical background and nature of the data before it is analysed. There are chapters on survival analysis, using illuminating case studies.

Abstract: Voltage sags, also known as dips, are important to industrial reliability. Modern process controls are often sensitive to voltage sags. The combination of voltage sags and sensitive equipment may cause significant production outages. Less sensitive equipment may be available, but the designer must know sag characteristics of the electric system to make the best choices between reliability and equipment cost. This paper shows how to predict voltage sag performance of electric supply systems by combining a new analysis method with reliability data. The analysis method is proposed for a new chapter in the next revision of IEEE Std 493. >

Abstract: This paper discusses the characteristics of noise sources in Al-based thin films and their relationships to VLSI reliability. Techniques of applying noise measurements in detecting existing defects/damages in the films, determining electromigration activation energy, and predicting the time to failure of VLSI interconnects are presented. The noise measurement technique can be applied to wafer-level reliability testing because it is much faster than the conventional MTF method and is nondestructive in nature. Some important considerations for wafer-level reliability testing via noise measurements are also presented in this paper. >

Abstract: Interconnection technology. Integrated circuits. Power sources and power supplies. Passive electronic components. Instruments and measurement. Heat management. Parasitic electrical and electromagnetic effects. Reliability and maintainability. Environmental factors and testing. Safety.

Abstract: No abstract available.

Abstract: The invention relates to a method and a device for adjusting parts operated by external force, especially in a motor vehicle bodywork, with increased reliability of an electrical sensor-controlled collision system. The invention can be used with particular advantage for electrically operated window lifters in motor vehicles and is characterised in that at least two redundantly operating sensors or sensor systems are used. Redundantly operating sensors which operate according to different physical principles are preferably used.

Abstract: A semiconductor device of the present invention accommodates a large semiconductor chip in a downsized package without impairing its reliability. The semiconductor chip is bonded on a relatively small die pad. Common inner leads and a plurality of inner leads are disposed opposite and spaced from the semiconductor chip by a gap ranging from 0.1 mm to 0.4 mm and the gap between the semiconductor chip and the common inner leads and the plurality of inner leads is filled with a resin which forms part of a resin package.

Abstract: We study reliable stabilization of linear, time-invariant, multi-input multi-output, two-channel decentralized control systems. We develop necessary and sufficient conditions for reliable decentralized stabilizability under sensor or actuator failures and present reliable decentralized controller design methods for strongly stabilizable plants.

Abstract: Two extensive communication satellite reliability studies were conducted in 1991 and 1993. These studies permitted a direct 'in-orbit' comparison at C-band between a thermionic electron device /spl lsqb/TWT/TWTA/spl rsqb/ and a solid state device /spl lsqb/GaAs MESFET/SSPA/spl rsqb/. Excellent performance, lifetimes and reliabilities for both types of microwave power amplifiers were obtained. However, surprisingly, both studies registered higher failure rates for SSPA's than TWTA's. >

Abstract: In this paper, a new approach is presented for estimating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user-specified deterministic input waveforms are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks. >

Abstract: In this paper we describe a hot-carrier and oxide reliability simulator, iProbe-d. In this program, a probabilistic timing approach is employed to find the most susceptible devices to hot-carrier degradation and/or oxide breakdown in a CMOS VLSI digital circuit design under expected operating conditions. After the damage in each device is determined, a combination of damaged-transistor model, RC delay and critical path analysis is used to estimate the impact of hot-carrier effects (HCE) on circuit performance; namely, the increase of circuit delay. The results can then be used to improve the reliability of the circuit prior to fabrication. >

Abstract: A vacuum CVD apparatus including a reaction chamber into which a fluorine-containing compound gas and a carrier gas are introduced for cleaning. The fluorine-containing compound gas reacts with the matter deposited on the inner surface of the reaction chamber to gasify and remove the matter, preventing contamination of a semiconductor wafer later placed in the reaction chamber. Thus, it is possible to achieve high reliability of VSLIs produced in the reaction chamber.

Abstract: Disclosed is a method of and an apparatus for evaluating the reliability of metal interconnects. It is capable of performing the evaluation under such a testing condition as to reproduce an actual operating environment, that is, under the testing condition of simultaneously accelerating electromigration and stress-induced migration, thereby evaluating failures conventionally missed to be evaluated. In particular, this method is applicable for evaluating the reliability of metal interconnects of semiconductor devices, and which includes the steps of performing a constant-temperature storage test I for interconnect reliability evaluation at a temperature over a specified temperature for a specified time; and applying a current to the interconnect and simultaneously performing a test II of measuring a voltage of the interconnect.

Abstract: The authors describe the reliability of silica-based PLC 1*8 splitters, which was investigated with reference to the Bellcore requirements. All of the 19 1*8 splitters that were tested satisfy the Bellcore optical criteria after 5000 h at 75 degrees C and 90% RH. >

Abstract: The yield and reliability requirements for multichip packaging (MCP) applications have provided the major impetus for the development of known-good-die (KGD) technology solutions. KGD technology includes components of electrical contact, mechanical fixturing, IC design, test and automation. This paper will provide an overview of the KGD market and KGD technologies currently available in the industry. Die-Level-Burn-In (DLBI) approaches based on temporary bare die carriers are emerging in the industry. The goal for carrier development for test and burn-in is a cost-effective, bare die contact and fixturing approach that accommodates both peripheral and array contacts as well as wire bond and bumped die. For semiconductor manufacturers, possibility of conducting burn-in in wafer form is more attractive and holds the promise of reducing the total cost to manufacture die, regardless of the packaging destination. This paper will provide a review of KGD technology solutions which span a range of maturity from conceptual to qualified for production.

Abstract: PURPOSE:To provide a capacitive acceleration detector which is improved in temperature characteristic, accuracy, and reliability and is sufficiently fit for use in a severe environment, such as the automobile, etc CONSTITUTION:The title detector is manufactured by sticking and fixing a sensor chip 1 for detecting acceleration to a circuit board 20 with adhesive layers 16 and 17 between which a spacer 21 is put Since the spacer 21 absorbs the deformation of the board 21 even when the board 20 warps due to a temperature change, the chip 1 receives no influence from the deformation of the board 20 and the characteristics of the chip 1 do not change Therefore, a highly reliable capacitive acceleration detector can be obtained

Abstract: The next generation of power semiconductor devices will be designed and optimized to meet the specific application requirements. Resonant dc link concept is gaining wide popularity in a range of soft-switching applications because of superior power conversion efficiency and improved overall system reliability. Mixed-mode simulations are used to study the carrier dynamics in non punchthrough IGBT structures during turn-off under soft- and hard-switching conditions. The simulation results are shown to qualitatively predict the measured bump in the tail current with varying output dv/dt conditions.

Abstract: PURPOSE:To provide a nonvolatile semiconductor memory device of high reliability which can surely avoid false recognition of data even if the number of rewritings is increased. CONSTITUTION:One memory cell is formed of two MOS transistors 30, 31 with floating gates 14, 15. In the two MOS transistors 30, 31, different logical levels are always input and output. If a pair of outputs obtained in this way are differentially amplified, false recognition of data caused by variation of threshold value of the MOS transistors 30, 31 can be avoided on judgment of '0', '1' of data of the memory cell.

Abstract: An anti-lock controller apparatus is constituted of a single microcomputer to reduce production costs and improve safety and reliability. Signals of wheel speed sensors S1 to S4 divided into two groups by an input processing circuit and are inputted to the single microcomputer. The single microcomputer executes two-system input/output processing and checks for abnormalities of the input/output signals.

Abstract: This paper presents a new high performance, reliable metal-to-metal antifuse The problem of switch-off in the programmed antifuses is avoided by using metals with low thermal conductivity and thin oxide >

Abstract: The reliability and availability of MV and HV circuit breakers is essential to the fulfilment of power network failure elimination. Experience has shown that about a quarter of major failures are due to failure of circuit breaker auxiliary and control circuits. Another important cause of failures is faulty SF/sub 6/ density monitoring systems. The integrity of this parameter is fundamental in ensuring the apparatus' dielectric rigidity as well as interruption of high fault currents. The last cause of major circuit breaker failures is the risk of failure of its mechanical parts. In order to solve these problems, the authors have undertaken the design of new low voltage auxiliary switchgear equipment with integrated state monitoring functions by making use of the new possibilities offered by appropriate digital equipment.

Abstract: Interconnections on silicon-based integrated circuits are almost exclusively aluminum alloys (Al-Si, Cu and various other solutes, e.g., Pd, Sc). The effects of film microstructure (grain size, grain size distribution, crystallographic texture and precipitate distribution) on the reliability of single level Al metallization has been well established. The final film microstructure obtained is dependent on both the deposition conditions and the thermal history during the manufacturing process. This paper will consider the role of microstructure in multi-level interconnects consisting of (1) AI(Cu) lines (in SiO2) with W and/or AI(Cu) studs and (2) an all Cu/polyimide multi-level structure. Methods for microstructure optimization during manufacturing of both Al and Cu based multilevel structures are explored. The variables important in determining the reliability of submicrometer single level versus multi-level structures and reliability testing methods (e.g., samples with versus without reservoirs and wafer level techniques) will be reviewed. Two relevant questions raised are; (1) What can be done during manufacturing to “build-in” reliability?, and (2) What are the trade-offs between manufacturing complexity (i.e., cost) and inherent reliability?

Abstract: PURPOSE:To miniaturize a flip chip connection semiconductor package, improve heat dissipating efficiency and electric characteristics, and realize cost reduction. CONSTITUTION:An IC chip 3 is bonded to the upper surface side of a printed wiring board 1 via flip chips 4, and resin sealed with sealing resin 5 by side potting. On the lower surface side of the printed circuit board 1, solder balls 6 whose melting point is lower than that of the flip chips 4 are arranged and heated. Hence solder bumps 7 for mother board connection are formed without fusing the flip chips 4. Thereby reliability of electric connection and heat dissipating efficiency are improved, and the cost reduction of a small-sized semiconductor package is enabled.

Abstract: An accelerated life testing reliability programme for miniature thermoelectric generators, fabricated using MOS processing technology, is described. From this, it is shown that the mean time to failure of a device is 5*104 h at the extreme of its normal operating range, i.e. 200 degrees C. The results of the programme also provide an insight into the failure mechanisms associated with miniature thermoelectric devices and enable the dominant mode to be detected. Consequently, the sections of the process sequence which would benefit from modification are identified.