Abstract: General techniques for predicting, reducing, and preventing problems associated with remote fault-clearing voltage dips are presented. The basic tools include a computer program to calculate unbalanced fault currents and voltages, reliability data, and fault-clearing device characteristics. Difficult calculations should be performed by any of several good analysis programs that are available. These programs can evaluate alternate configurations to optimize system performance. These techniques allow engineers to anticipate and possibly prevent voltage dip problems. Suggestions for coping with voltage dips that cannot be eliminated are offered.< >

Abstract: Projection indicates that by the turn of the century microcomputer chips will have 100 million transistors and failure rates of less than 10 FIT Traditional accelerated product life tests and wafer level reliability measurement techniques being developed at present will have severe limitations in resolving the 10 FIT failure rate of complex VLSI circuits This paper discusses these limitations along with the change in direction that the reliability engineering and manufacturing community will have to take over the next decade to meet the challenge of continuously decreasing failure rate goals

Abstract: Let Y 1 , · ··, Y n be a finite Markov chain and let f be a binary value function defined over the state space of the Y 's. We study the reliability of general series system having the structure function φ ( Y ) = min { f ( Y 1 ), · ··, f ( Y n )} and show that, under certain regularity conditions, the reliability of the system tends to a constant c (1 ≥ c ≥ 0), where c often has the form c = exp {– λ }.

Abstract: The motivation, challenges, and status of IC reliability simulation are discussed. The reliability simulator BERT (Berkeley Reliability Tool) is used to illustrate the physical models and approaches used to simulate the hot electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation. >

Abstract: Given the devastating consequences of nuclear war, it is appropriate to look at current and planned uses of computers in nuclear weapons command and control systems, and to examine whether these systems can fulfill their intended roles.

Abstract: A study is presented on the effects of voltage scaling on hot-electron phenomena and intrinsic device performance in submicrometer MOSFETs. A Monte Carlo device simulator featuring a suitable band model for high-energy electrons is used. An interesting finding is that at very short channel lengths the high energy tail of the electron distribution function, the most important quantity in determining hot-carrier reliability, is controlled by the applied bias and not by local electric fields. As confirmed by recently reported experimental work, the results of this study indicate that the conventional, linear voltage scaling can be weakened using a more relaxed voltage reduction law that leads to improved performance without threatening device reliability. >

Abstract: A large, high-voltage switched reluctance motor that benefits from the more reliable concentration stator winding with regard to switching surges is presented. The easy-to-build rotor construction enhances reliability. Details of the high-voltage winding are presented, together with performance predictions. Prospects for even larger machines are discussed. >

Abstract: Interpretation of highly accelerated life test (HALT) failure data requires the use of the correct statistics. Wiebull and log-normal distributions were compared to the exponential distribution. While the exponential is a special case of the Wiebull, the log-normal was found to be sensitive to secondary populations which have a significant influence on the early life of the capacitor. These populations may have predicted lifetimes up to 20 years, and are thus significant. The effect of increased temperature and voltage on the acceleration factors normally used by industry is investigated. From these, criteria for burn-in and failure rate determination can be determined which would provide the user with a measure of reliability of the product being used. Some of the factors which affect the results can be related to process conditions so that a measure of manufacturing process capability is also obtained. >

Abstract: An electrical technique is described which can perform a fast measurement of the peak junction temperature of power transistors. The fundamental principles of this technique are summarized as three modifications to the standard electrical technique for measuring the junction temperature. Personal-computer-controlled equipment has been developed based on these principles. In comparison with the infrared-measured peak junction temperature, the measuring error of the equipment is within 8%, whereas the error of the standard electrical method may be up to 50% under the same conditions. The equipment reported here can provide convenience for device manufacturers and users in evaluating device thermal behavior and conducting reliability screening. >

Abstract: PURPOSE: To provide a laminated capacitor having excellent temperature stability, a small size and a large capacity by solving problems of decreases in dielectric loss, insulating resistance, reproducibility and reliability when the size is reduced and the capacitance is increased in the capacitor to be used for various electronic apparatuses CONSTITUTION: A heat generator for controlling the temperature of an element constant is formed at a capacitor body in which dielectric layers 2 and metal conductors 1 are alternately laminated in a laminated ceramic capacitor The capacitor having excellent temperature stability, a small size and a large capacitance which have heretofore been difficult is obtained COPYRIGHT: (C)1993,JPO&Japio

Abstract: PURPOSE:To provide the title reliability evaluating and testing device capable of automating the sequences thereof such as burn-in inspection, etc. CONSTITUTION:A test station 4 is arranged on the inner wall surface of a constant temperature bath 1 and then a conveyer belt 6 fitted with multiple carriers 5 is stretched over sprockets 7 to be carried on the specific path inside the constant temperature bath 1. At this time, respective carriers 5 are fitted with semiconductor devices 8 impressed with specific voltage from a burn-in power supply through the conveyer belt 6 so that thermal and electrical stresses may be imposed on the semiconductor devices 8. Thus, the semiconductor devices 8 aged for specific time are successively carried to the position of the test station 4 to take the specific tests by a tester 3. Through these procedures, the semiconductor devices 8 need not be taken out of the carriers 5 thereby enabling the devices 8 to repeat the aging step and the electrical test continuously.

Abstract: A wire bonding external appearance inspecting apparatus for inspecting wires bonded to a semiconductor chip and the vicinity thereof, comprises a plurality of illuminating units of different illumination directions, for illuminating the semiconductor chip and the vicinity thereof, and a controller for selecting and operating any one of the plural illuminating units according to the inspection places thereof. Since an optimum illumination can be obtained according to inspection items, a camera can take plural different images according to objects to be inspected, so that the inspection reliability can be improved.

Abstract: A system and method for controlling plural load with high reliability, comprising plural control devices for respectively controlling the plural electric loads, plural switches for respectively giving ordering signals to the control devices to control the respective loads, and a monitor circuit for detecting an out of order control device and generating ordering signals for selecting another control device which is not out of order based on the superiority of the other electric load and the ordering signals from the switches which correspond to the other control device to change from the control device which is out of order to the other control device.

Abstract: A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator is presented along with a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback. Simulation speedup of 3N over SPICE-like simulators has been observed, where N is the number of transistors. The simulator is able to simulate circuits as large as 235000 transistors in 10 min real time. Also presented is a novel approach to fast hot-carrier reliability simulation. These methods make it possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with as many as hundreds of thousands of MOS transistors in a workstation environment. >

Abstract: It is demonstrated that AC supply current analysis can be an effective method for testing complex digital devices in a technology other than CMOS. Experiments using a microprocessor demonstrate the effectiveness of this approach and its potential for reliability analysis and mixed-signal testing. Results from two different methods of waveform analysis are presented. The application of statistical signal detection methods is shown to provide superior fault detection, compared to AR (autoregressive) modeling. Because the signature is analyzed as a continuous-time signal and no assumptions are made regarding waveform shape or fault effects, it is believed that this method may be applied to the testing of both digital and analog devices, at various levels of integration. An additional benefit may be the capability of detecting minor current aberrations, resulting from activated failure mechanisms prior to functional failure. >

Abstract: It is shown that microelectronic failures which occur within equipment operating temperature extremes are not dependent on absolute temperature! Therefore, tremendous equipment reductions can be made in size, weight and cost, and there will be an improvement in reliability by elimination of failures due to unreliable complex cooling systems.

Abstract: The authors describe features of the design and operation of a strontium vapour laser in which strontium vapour is injected into the discharge from a thermostatically controlled external reservoir. This allows the vapour pressure to be regulated independently of all other parameters of the discharge, providing much greater control over the laser as well as considerably improved reliability compared with self-heated devices. The authors also report the dependence of the average output power on vapour pressure and other parameters.

Abstract: PURPOSE: To prevent the deterioration of CCB connecting section, to improve reliability, to attain high density packaging, to enable the usage of a wafer manufacturing process and to enhance the accuracy of finishing and yield on manufacture in a semiconductor integrated circuit device. CONSTITUTION: In a semiconductor intagrated circuit device, an Si wafer 1a, which is formed of the same Si as an LSI chip 2 and in which through-holes 3 are formed, is used as a package substrate 1. COPYRIGHT: (C)1992,JPO&Japio

Abstract: A self-testing and mutual testing method of multifunctional remote control transmitters includes the steps of self-testing multifunctional remote control transmitters by selecting a self-testing mode using a test pin switch, mutually testing multifunctional remote control transmitters by selecting a mutual testing mode, compressing and analyzing data by the multifunctional remote control transmitters, and displaying the error condition. The method facilitates checking faults occurring in multifunctional remote control transmitters, thereby reducing poor products and enhancing the reliability of the products.

Abstract: The reliability of silicon integrated circuits (ICs) has improved significantly in the last decade. The complexity of ICs continues to increase. The semiconductor industry is actively working to a) improve the reliability of very large scale (VLSI) ICs, and b) reduce the failure rates to a value closer to 0.1 FIT by the year 2000. This paper summarizes the current status of quality and reliability of ICs. Some of the reliability limiting factors are described. Inadequacy of conventional accelerated test methods to verify the reliability of VLSI devices is highlighted. A challenging VLSI reliability goal with a failure rate approaching 0.1 FIT requires a) an understanding of the root causes of failure mechanisms, b) a translation of the lessons learned into a set of design rules for the circuit designers, c) appropriate materials and process specifications consistent with manufacturing capabilities, and d) in-process reliability test structures and test procedures. A VLSI failure rate goal of 0.1 FIT presents an exciting challenge for the materials scientists.

Abstract: Voltage supply scaling for a BiCMOS gate was investigated experimentally and analytically. For half-micrometer technology, the supply voltage design tradeoffs between propagation delay and NMOSFET reliability were studied. It was found that the minimum BiCMOS operating voltage ranges from 2.5 to 3.0 V. This minimum can be explained by the sum of twice the base-emitter potential and the NMOSFET threshold voltage, due to the emitter grounded Bi-MOS structure of the BiCMOS gate. As a result, 3.3-V operation is inherently marginal for BiCMOS gates. On the other hand, NMOS reliability in the BiCMOS gate is drastically improved because effective drain voltage is reduced by the base-emitter potential. Thus, NMOSFETs with a channel length shorter by more than 0.2 mu m can be used, and this ensures reliable operation of BiCMOS gates at 5 V. In terms of the tradeoffs between gate speed and NMOS reliability, it is verified that BiCMOS gates offer the highest speed in half-micrometer design. >

Abstract: PURPOSE:To enhance reliability by a method wherein a pressure load is adjusted accurately by means of an output of a load detection part CONSTITUTION:A computing and control part 28 outputs an instruction signal 29 to a servomotor 23 on the basis of a detection signal 27 of a load detection part 26; it adjusts a driving mechanism part 14 and controls a bonding tool 13 in such a way that an actual pressure load becomes equal to a set load according to the characteristic of a semiconductor chip 18 Consequently, it is prevented that the pressure load exerted on the chip 18 is changed with a change in the temperature condition of the tool 13; the pressure load can be kept definite irrespective of thermal expansion of the tool 13 When the chip 18 is cooled after its heating has been finished, the driving force of the mechanism part 14 is adjusted, the pressure load is kept definite and a bonding operation can be executed under a prescribed load condition even when a bonding material for bumps 19 is contracted and its hardness and its volume are changed Thereby, the bonding operation which is sure and whose reliability is high can be executed

Abstract: The authors report newly developed Ku-band super-low-noise pseudomorphic heterojunction FETs (HJFETs) with high producibility and high reliability, utilizing a novel electron beam lithography technique. The developed HJFETs with 0.25 mu m long and 200 mu m wide gate FETs showed an average noise figure of 0.6 dB with 11.3 dB average associated gain at 12 GHz and exhibited highly reliable operation with a mean time to failure of 3*10/sup 9/ hours at 100 degrees C. >