Showing papers on "Reliability (semiconductor) published in 1990"
TL;DR: The chapter summarizes analytical, numerical, and experimental work in literature, in order to facilitate the improvement of existing schemes and provide a basis for the development of new ones on the thermal control of semiconductor devices, modules, and total systems.
Abstract: Publisher Summary Thermal control of electronic components has one principal objective, to maintain relatively constant component temperature equal to or below the manufacturer's maximum specified service temperature, typically between 85 and 100°C. It is noted that even a single component operating 10°C beyond this temperature can reduce the reliability of certain systems by as much as 50%. Therefore, it is important for the new thermal control schemes to be capable of eliminating hot spots within the electronic devices, removing heat from these devices and dissipating this heat to the surrounding environment. Several strategies have developed over the years for controlling and removing the heat generated in multichip modules, which include advanced air-cooling schemes, direct cooling, and miniature thermosyphons or free-falling liquid films. The chapter summarizes analytical, numerical, and experimental work in literature, in order to facilitate the improvement of existing schemes and provide a basis for the development of new ones. The chapter focuses on investigations performed over the past decade and includes information on the thermal control of semiconductor devices, modules, and total systems.
302 citations
TL;DR: An overview of semiconductor-based and superconductor-based low-temperature electronics is presented in this paper, where the issues of reliability and thermal expansion mismatch are discussed.
Abstract: An overview of semiconductor-based and superconductor-based low-temperature electronics is presented. The general issues of reliability and thermal expansion mismatch are discussed. The discussion of semiconductor electronics starts with a description of a cryogenic supercomputer, the ETA, and then covers devices and materials, noise and applications to signal processing for sensors. Superconductor electronics is then discussed, including signal processing, digital systems, and oscillating junctions. The success of electronics with small numbers of Josephson junctions and the outlook for higher-temperature operation are addressed. Hybrid applications, combining semiconductor and superconductor technologies at the device, circuit, or system level, are examined, highlighting the problems of electrical interfacing and interconnections. >
147 citations
TL;DR: In this paper, the effect of time-dependent stress voltage and temperature on the reliability of thin SiO/sub 2/ films is incorporated in a quantitative defect-induced breakdown model, design curves which can be used along with a breakdown voltage distribution for an oxide technology to determine optimal burn-in conditions are presented.
Abstract: The effect of time-dependent stress voltage and temperature on the reliability of thin SiO/sub 2/ films is incorporated in a quantitative defect-induced breakdown model. Based on this model, design curves which can be used along with a breakdown voltage distribution for an oxide technology to determine optimal burn-in conditions are presented. The tradeoff between improved reliability and lower burn-in yield for different gate oxide technologies can also be examined quantitatively using the model. >
123 citations
Patent•
6 Jul 1990TL;DR: In this paper, the authors present a method for manufacturing a highly reliable semiconductor device without waste by incorporating predetermined functions into a wafer in wafer completion process, aging the wafer, distinguishing between non-defective and defective chips in a probe inspection process, separating chips in the waf one by one in a dicing process, sorting out the chips into nondefective, defective and selection process, then analyzing failure information and feeding back the result of the analysis to the WFC in a feedback process, thereby quickly analyzing and repairing a failure process on reliability.
Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device without waste by incorporating predetermined functions into a wafer in a wafer completion process, aging the wafer in a wafer aging process, distinguishing between non-defective and defective chips in a probe inspection process, separating chips in the wafer one by one in a dicing process, sorting out the chips into non-defective and defective chips in a selection process, then analyzing failure information and feeding back the result of the analysis to the wafer completion process in a feedback process, thereby quickly analyzing and repairing a failure process on reliability in the wafer completion process.
79 citations
27 Mar 1990
TL;DR: In this article, the authors discuss the limitations of traditional product life tests and wafer-level reliability measurement techniques in resolving the 10 FIT failure rate of complex VLSI circuits and the change in direction that the reliability engineering and manufacturing community will have to take over the next decade to meet the challenge of continuously decreasing failure rate goals.
Abstract: Projection indicates that by the turn of the century microcomputer chips will have 100 million transistors and failure rates of less than 10 FIT. Traditional accelerated product life tests and wafer-level reliability measurement techniques presently being developed will have severe limitations in resolving the 10 FIT failure rate of complex VLSI circuits. These limitations are discussed, along with the change in direction that the reliability engineering and manufacturing community will have to take over the next decade to meet the challenge of continuously decreasing failure rate goals. >
51 citations
TL;DR: In this article, the tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometers gate lengths, taking into account high-field effects on MOSFETs.
Abstract: The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). >
43 citations
Patent•
14 May 1990
TL;DR: In this article, the authors present an approach and methods for facilitating insertion and maximizing resiliency, reliability and conductivity of button contacts in button board type circuit interconnectors.
Abstract: Apparatus and methods for facilitating insertion and maximizing resiliency, reliability and conductivity of button contacts in button board type circuit interconnectors.
40 citations
40 citations
11 Nov 1990
TL;DR: A novel method for an efficient estimation of the current waveforms of complex CMOS macro cells or modules at the gate level is presented and a prototype computer program-SIMCURRENT-based on this method runs about 5000 times faster than state of the art analog circuit simulators.
Abstract: A novel method for an efficient estimation of the current waveforms of complex CMOS macro cells or modules at the gate level is presented. A prototype computer program-SIMCURRENT-based on this method runs about 5000 times faster than state of the art analog circuit simulators. The accuracy of the current estimation is in the range of about 5%-mean and rms current values-based on simulation results. The investigations are based on actual double layer Al CMOS processes used in industry. The SIMCURRENT program enables the proper layout of power rails which fulfil mean and peak current limits for electromigration. These limits are derived from reliability calculations for the given process. Simulation results for various circuits are presented. >
31 citations
11 Nov 1990
TL;DR: A novel integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance, which incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors.
Abstract: A novel integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model used in the simulation tool includes both of the fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. The simulation tool provides information on the evolution of device degradation during long-term operation, and on the performance characteristics of the damaged circuit. >
20 May 1990
TL;DR: A plated solder-bump process used for the manufacture of high-reliability flip chips is described in this article, where detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described.
Abstract: A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to 1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance. >
1 Jan 1990
TL;DR: In this article, the effect of time-dependent stress voltage and temperature on the reliability of thin SO2 films is incorporated in a quantitative defect-induced hreakdnwn model.
Abstract: Ahstrod-The effect of time-dependent stress voltage and temperature on the reliability nf thin SO2 films is incorporated in a quantitative defect-induced hreakdnwn model. Rased on this model, design curves are presented which can be used along with a hreakdown vnltage distrihution for an oxide technology to determine nptimal hurn-in cnnditions. The tradenff between improved reliability and lnwer hurnin yield for different gate oxide technnlngies can also he examined quantitatively using the model presented here.
Patent•
2 Nov 1990
TL;DR: In this article, a semiconductor pressure sensor device comprising a housing having a cavity, a sensor chip mounted within the cavity, leads for conveying pressure detection signals, and bonding wires electrically connecting the sensor chip and the leads, a sensitive portion (2 a ) of sensor chip (2 ), leads (4 ) and wiring wires (6 ) are covered with an electrically insulating fluorochemical gel material which has a penetration of 30-60 according to JIS K2220.
Abstract: In a semiconductor pressure sensor device comprising a housing ( 1 ) having a cavity ( 3 ), a semiconductor sensor chip ( 2 ) mounted within the cavity, leads ( 4 ) for conveying pressure detection signals, and bonding wires ( 6 ) electrically connecting the sensor chip and the leads, a sensitive portion ( 2 a ) of sensor chip ( 2 ), leads ( 4 ) and bonding wires ( 6 ) are covered with an electrically insulating fluorochemical gel material which has a penetration of 30-60 according to JIS K2220, a Tg of up to −45° C., and a degree of saturation swelling in gasoline at 23° C. of up to 7% by weight. The sensor device is improved in operation reliability and durability life.
23 Jan 1990
TL;DR: A physics-of-failure approach to reliability prediction for integrated circuits is discussed in this article, based on the expectation that no integrated circuit can ever be free of imperfections and the assumption that both microscopic (point) defects and macroscopic flaws play influential roles in determining IC reliability.
Abstract: A physics-of-failure approach to reliability prediction for integrated circuits is discussed. The analysis described is based upon the expectation that no integrated circuit can ever be free of imperfections and the assumption that both microscopic (point) defects and macroscopic flaws play influential roles in determining IC reliability. It is demonstrated that the microscopic defects can be directly implicated in gradual degradation over time via analyses related to those used in modeling a variety of solid-state phenomena. >
27 Mar 1990
TL;DR: In this paper, a model for predicting interconnect electromigration time-to-failure under arbitrary current waveforms is shown to be applicable to Al-W intermetallic contacts as well.
Abstract: A previously developed model for predicting interconnect electromigration time-to-failure under arbitrary current waveforms is shown to be applicable to Al-W intermetallic contacts as well. This model is incorporated in a circuit electromigration reliability simulator which can (1) generate layout advisory for width and length of each interconnect, the safety factor of each contact and via in a circuit to meet user-specified reliability requirements and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure. >
TL;DR: In this article, a review is made of compound semiconductor device reliability from the period 1980 to the present, focusing on technology based on field effect transistors (FETs).
Abstract: A review is made of compound semiconductor device reliability from the period 1980 to the present. Emphasis is placed on technology based on field effect transistors (FETs). Many reliability studies were made of small signal GaAs FETs in the 1970s and of GaAs power FETs in the 1980’s; a substantial reliability base exists for these devices. However, there remains a lack of reliability data for GaAs devices such as digital ICs, MMICs, and heterojunction transistors (HEMTs, HBTs). Future directions for high reliability lie in device designs to reduce channel and junction temperatures, reduction in interdiffusion and ion migration between metal/semiconductor layers and between semiconductor layers, and in the development of high temperature stable Schottky barrier metallizations and Ohmic contacts.
4 Jan 1990
TL;DR: High-risk organizations are high risk in the sense that errors in them may lead to catastrophic consequences.
Abstract: Abstract Among high technology organizations there is a set of organizations labeled “high risk” (Perrow, 1984). They are high risk in the sense that errors in them may lead not only to employee death or to the need to rebuild parts of the organization, but to catastrophic consequences of such magnitude that they are unacceptable to the organization or a larger public. For example, the result of the accident at Union Carbide’ s chemical plant at Bhopal in 1984 is unacceptable to the Indian government.
27 Mar 1990
TL;DR: In this article, four areas for achieving a stable, reliable process in a high volume environment are considered: (a) process capability in a manufacturing environment; (b) manufacturing control; (c) assessment of process interactions; (d) process monitoring.
Abstract: Four areas for achieving a stable, reliable process in a high volume environment are considered: (a) process capability in a manufacturing environment; (b) manufacturing control; (c) assessment of process interactions; (d) process monitoring. These areas are discussed, and suggestions for their application are made. >
01 Jan 1990-International Journal of Radiation Applications and Instrumentation. Part C. Radiation Physics and Chemistry
TL;DR: The IMPELA electron accelerators are derived from a common basic design of rf accelerating structure which is capable of handling beams with powers from 20 to 250 kW at 5 to 18 MeV.
23 Jan 1990
TL;DR: In this article, a reliability model for a repairable standby system with imperfect sensing and switching units is developed, where two unequal units have energized as well as quiescent failure rates and have corresponding repair rates.
Abstract: A reliability model for a repairable standby system with imperfect sensing and switching units is developed. The system has two unequal units which have energized as well as quiescent failure rates and have corresponding repair rates. The system has a sensing unit with a nonzero failure rate and a switching unit which has both cyclic and continuous failure rates, with the continuous mode including failing-open and failing-closed function modes. The system's reliability is obtained in an explicit form. Numerical examples are given, and the effects of the sensing and switching unit's failure rates on the system's reliability are discussed. >
TL;DR: The integration of a process simulator with a commercial computer-aided manufacturing (CAM) system to provide a set of powerful tools for process analysis, diagnosis, and control is described.
Abstract: The integration of a process simulator with a commercial computer-aided manufacturing (CAM) system to provide a set of powerful tools for process analysis, diagnosis, and control is described. The CAM system acts as the interface to the simulator and maintains the simulation control data as part of the process specification. Making process simulation available in a manufacturing environment allows engineers to intuitively investigate the process, thus aiding their understanding of the interrelation of process steps. A microprocessing scenario in an application-specific integrated circuit (ASIC) facility is used to demonstrate how the system can be used to analyze options for corrective processing. It can also be used for documenting processes, to simplify process transfer and implementation, and for investigating the effect of corrective processing on device reliability. >
13 May 1990
TL;DR: The use of reliability assurance and enhancement of integrated circuits in the design of high-performance electronic systems is discussed and circuit simulators with embedded degradation models can be utilized to accurately predict VLSI reliability due to hot-carrier effects and electromigration.
Abstract: The use of reliability assurance and enhancement of integrated circuits in the design of high-performance electronic systems is discussed. Circuit simulators with embedded degradation models can be utilized to accurately predict VLSI reliability due to hot-carrier effects and electromigration. Basic design methods for constructing digital and analog circuit blocks with adequate built-in reliability are presented. Lifetime for DRAM circuitries and operational amplifiers can be significantly increased through these novel simulation techniques. Several practical VLSI design examples using an integrated-circuit reliability simulator are discussed. >
TL;DR: In this article, the development of the four main types of electronic capacitors (aluminum electrolytic capacitors, ceramics, tantalum and film capacitors) is discussed.
Abstract: The technological development of the four main types of electronic capacitors-aluminum electrolytic capacitors, ceramic capacitors, tantalum electrolytic capacitors, and film capacitors-are discussed. Particular attention is given to the materials involved and the accompanying innovations in manufacturing techniques, which have enabled electronic capacitors to move steadily toward miniaturization, longer life, lower prices, and improved reliability. >
TL;DR: In this paper, the design of the Space Station Freedom's electric power system (EPS) is reviewed, highlighting the key design goals of performance, low cost, reliability, and safety.
Abstract: The design of Space Station Freedom's electric power system (EPS) is reviewed, highlighting the key design goals of performance, low cost, reliability, and safety. The EPS design is divided into three separate areas: power generation and storage, power distribution, and power management and control. Both photovoltaic and solar dynamic power generation and storage systems are used. Tradeoff study results that illustrate the competing factors responsible for many of the more important design decisions are discussed. Reliability and maintainability, as well as verification and testing, are addressed. >
TL;DR: In this paper, a small and thin quad flat package (QFP)-type plastic package for large-scale integrated (LSI) logic devices with high pin counts has been developed.
Abstract: A small and thin quad flat package (QFP)-type plastic package for large-scale integrated (LSI) logic devices with high pin counts has been developed. The size of the package with 252 input and output pins is 17.3 mm by 17.3 mm, and the thickness is 1.52 mm. The pitch and the width of the leads are 0.25 and 0.1 mm, respectively. The main technologies for assembly of the package are tape automated bonding (TAB) interconnection technology, which has been developed for bonding of high-terminal-count LSIs, and the molding technology, which has also been developed for very small and thin plastic packages. The reliability of the package and the outer lead bonding of the package were evaluated, and it was confirmed that both the package and the bonding have no problem in the pressure cooker test (PCT), the temperature cycle test, and the high-temperature-storage test. >
TL;DR: The reliability of HEMT I.C. circuits has been investigated in this paper, showing that the enhancement mode circuits are the weak point in the circuit's reliability, while the primary degradation mode is confinement of the 2DEG channel and various lateral diffusion effects, which occur during circuit operation.
Abstract: The reliability of HEMT I.Cs indicates that the enhancement mode circuits are the weak point in the circuit’s reliability. Rapid degradation, has been observed at temperatures above 200°C. The HEMT I.C. reliability results tend to follow the enhancement mode degradation statistics. The primary degradation mode is the confinement of the 2DEG channel and various lateral diffusion effects, which occur during circuit operation.
TL;DR: The application of E-beam testing coupled with Ion-beam circuit repair ie modification during prototype development, used in conjunction with X-ray radiography,X-ray microanalysis, electron imaging techniques and the use of acoustic microscopy techniques for quality control are discussed in this paper.