Abstract: The importance of the mean operating temperature of a monolithic integrated circuit encapsulated in a molded plastic package and its relation to the reliability of that component is reviewed. A thermal model of a plastic package is described and experimentally verified. The model is applied to measure chip or junction temperature under operating conditions, and errors which can be introduced are discussed.

Abstract: The theory and technology of equipment aging is reviewed, particularly as they relate to the qualification of safety-system equipment for nuclear power generating stations. A fundamental degradation model is developed, and its relation to more restricted models (e.g., Arrhenius and inverse-stress models) is shown. The most common theoretical and empirical models of aging are introduced, and limitations on their practical application are analyzed. Reliability theory and its application to the acceleration of aging are also discussed. A compendium of aging data for materials and components, including degradation mechanisms, failure modes and activation energies, is included.

Abstract: Physical defects, such as cracks, spa!Is, and delaminations, may be associated with a significant percentage of the multilayered capacitors produced for high reliability applications. These defects may lead to severe cracking of the capacitors and eventually to their electrical failure. This paper presents a fracture mechanics approach to the reliability assessment of physically defective capacitors used under high mechanical stress conditions. This approach requires both the characterization of the material properties (fracture toughness, elastic moduli, et cetera) of the multilayer capacitor and of the part's application (environment and operational conditions). From these results the mechanical reliability of a capacitor can be estimated for different system applications and realistic limits can be determined for the allowable sizes and types of defects.

Abstract: The use of accelerated step-stress and constant stress-in-time test techniques is demonstrated for generating models for predicting reliability at use conditions. Reliability prediction models were obtained for a signal diode, signal and power transistors, silicon trolled rectifier, and metal oxide varistor. Each of these device types follows the Arrhenius model for reliability prediction. Techniques are demonstrated for determining 1) the acceleration factor between extremely high acceleration testing conditions and field operating conditions on the signal diode; and 2) the acceleration or multiplying factor between high level stresses and use conditions which can be used to predict the performance of the signal diode over time. The effect of relative humidity on reliability is discussed. Devices under power operation have a lower relative humidity (RH) than the environment. This low RH suppresses humidity activated mechanisms. A transistor high-reliability screen which removes devices with early manufacturing type defects is described. This screen was effective, efficient and economical for improving the reliability of systems. A technique of combining acceleration factors for a number of items which affect reliability was demonstrated for the diode. This same technique should be useful for most device reliability predictions. The acceleration factors, however, can not be extrapolated into stress levels much above maximum ratings where new failure modes may appear that override the established failure rate relation with stress. The straight line plots of failure rates in this paper are terminated before these threshold limits.

Abstract: 1. Specifications. 2. Reliability. 3. Electronic components. 4. Digital logic circuits. 5. Circuits using linear integrated circuits. 6. Power supply and power control circuits. 7. Testing methods and ATE. 8. System maintenance and fault diagnosis. 9. An introduction to microprocessor based system testing.

Abstract: This paper is principally concerned with the implications of FCL reliability upon the design and application of fault current limiters. The paper examines the following important questions: I) Can devices which are designed to meet present functional specificationis for fault current limiters be made compatible witlh the implicit need for reliability and economy? 2) Sinice no device will ever be fully reliable, what are the consequenices of FCL failure, anld what constitutes reasonable backup protectioni? 3) Cain the nieeds whlichi have spawned the quest for the FCL be met better in a manner more consistent with the essential needs for economy and reliability by modifying the functional specifications? t 4) For puirposes of backup protection, would a limiter which responds only after the first current loop has been allowed to pass be of any worth? 5) Are there any significant improvements or benefits in the tolerance of apparatus to momentary currents if severe fault currents are limited to a single current loop?

Abstract: This paper discusses the development of an improved failure-rate prediction method which can be used to assess the reliability of complex and new-technology microcircuits, especially memories, microprocessors, and their support devices. The prediction models are similar to those presented in MIL-HDBK-217C with several modifications to reflect the variation of reliability sensitive parameters and to discriminate against the device design and usage attributes which contribute to known failure mechanisms. A comparison of the failure rate predictions calculated using MIL-HDBK-217C and the actual failure rates for LSI random logic and memory devices did not indicate a reasonable correlation. An analysis of the 217C models revealed that the lack of correlation was attributable to the generic consolidation of model parameters, which ultimately reduced model sensitivity to several critical reliability factors. The model accuracy was greatly improved, without substantially increasing model complexity, by separating some generic parameters into sets of more detailed parameters. The major model revisions included: ? Complexity factors oriented toward major device function and technology categories ? Development of temperature factors for each device technology, in both hermetic and nonhermetic packages ? Introduction of an additive package failure-rate factor based upon package type and number of functional pins ? Introduction of a voltage derating stress factor for CMOS devices with maximum recommended operating supply voltage greater than 12 volts ? Introduction of a ROM and PROM programming technique factor to reflect the influence of the programming mechanism used in these devices.

Abstract: Reliability prediction of MOS LSI devices by testing at elevated temperature can be influenced by electrostatic discharge and electrical overstress conditions during the test period. MOS devices that used junction diodes in the input protection structure were found to be more susceptible to failure from electrostatic discharge in 125°C ambient temperature than at 25°C. Failure analysis and modeling indicate that this effect is more severe for MOS LSI devices than for bipolar devices due to the doping levels used in the MOS technology. These effects will impact accelerated life testing, simulation testing of electronic systems to be operated at elevated temperatures and failure analysis techniques performed at elevated temperatures.

Abstract: The problem of simultaneous striking of coupled tubes which are electrically in parallel but optically in series, used in a moderate power coaxial CW-CO2 laser is discussed. The paper describes a circuit using SCRs to strike the coupled tubes simultaneously with very good reliability.

Abstract: As electronics begins to play an ever increasing role of importance in automotive electronics, so the demand for higher reliability becomes ever more evident. This reliability must be assured under conditions which, for electronic devices, are severe to say the least.

Abstract: PURPOSE:To restrain the lowering of a processing efficiency to a minimum to realize a high reliability dependent upon double recording by recording the same data on two disc devices duplicately and reporting the write end to the upper-level device at a write end time. CONSTITUTION:Receiving a write command, a disc control unit transfers the whole or a part of data to be written to data buffer 3 if the command can be executed. After that, this data is written onto two disc devices A and B which are designated previously and are not rotated synchronously. A signal is sent to write end control circuits 4 and 5 each time write is completed in devices A and B; and when circuits 4 and 5 decides that the write to devices A and B is completed, the write of contents of buffer 3 is regarded as completed. Therefore, write is performed, as it were, to one disc device at the view from software, so that double write is possible without increasing the processing time.

Abstract: PURPOSE:To reduce the number of parts for reducing the cost and also improve the reliability by interlocking a disc as an on-off timer for intermittently causing high frequency oscillation to a rotative shaft of a rotary shelf 5 serving to support the material to be heated.

Abstract: PURPOSE:To effect measurement simple and high in reliability on a compound semiconductor single srystal for resistance distribution by a method whrerin said single crystal wafer is soaked in a coolant, at least two pieces of probes are contacted with the wafer surface at given intervals under a constant pressure, and then current is carried between the probes. CONSTITUTION:A compound semiconductor single crystal wafer 14 is soaked in a coolant 15. Next, at least two pieces of probes 19a, 19b are contacted with the surface of the wafer 14 at given intervals under a constant pressure. Then, a current is carried between lead wires 20a, 20b from an external supply to measure resistance between portion of the wafer 14 with which the probes 19a, 19b are contacted. After the first measurment for resistance is over, the probes 19a, 19b are moved upward by operating a slide shaft 23 to slide to a given spot, they are again contacted with the wafer 14 to a measurement of resistance values as described above.

Abstract: Molybdenum, which is widely used in the electronics industry, is usually a misunderstood metal. An introduction to its manufacture and present use is presented. The new development of cladding molybdenum with various materials and/or elements, which not only improves the reliability of the electronic device but also reduces production costs, is described.

Abstract: CMOS electrostatic discharge (ESD) failures in a product where, by design, the device input terminals are not accessible to ESD led to this study of device susceptibility and an analysis of the long-term reliability of devices in assemblies from that production line. Some surprising patterns of device susceptibility are established and it is shown that the probability of long-term failure in devices whose electrical characteristics have been degraded by electrostatic discharge is small.

Abstract: An example of how modern engineering and safety techniques can be used to assure the reliable and safe operation of photovoltaic power systems is presented. This particular application is for a solar cell power system demonstration project designed to provide electric power requirements for remote villages. The techniques utilized involve a definition of the power system natural and operating environment, use of design criteria and analysis techniques, an awareness of potential problems via the inherent reliability and FMEA methods, and use of fail-safe and planned spare parts engineering philosophy.

Abstract: In a reliability test for semiconductor devices, a second conductor track plane is defined to the first and allocated to the chips which remain assembled in the first. The chips receive the temp./voltage overloads via this second plane. The latter is then etched away and the normal wafer test can be carried out for the assembly to determine any parameters which may have been affected by a drift due to the overload test. The result is a great saving in expenditure for testing (20% excess voltage and temp. for 24 hrs.) because the reliability test is carried out when 300-1000 chips are still assembled on a board for simultaneous test.

Abstract: PURPOSE:To increase reliability and reduce the size of devices, by packaging semiconductor devices evenly by means of film-form packaging material. CONSTITUTION:While band-shaped base film 3 fitted with many semiconductor devices 1 at fixed intervals is being transported, band-shaped film 7 is bonded to both surfaces of base film 3 in succession under heating and pressure, and thereby semiconductor devices 1 are packaged.

Abstract: PURPOSE:To improve the reliability by constituting the thermal responsive switch such that the opening speed of movable contact against the fixed electrode becomes lower than specific level thereby reducing the fluctuation. CONSTITUTION:When the switching speed of movable contact 10 exceeds over 0.2mm/sec, pulse generating time is as low as 1-2 and doesn't depend on the switching speed of movable contact 10. Consequently when the switching speed of movable contact 10 during the thermal responsive switch 12 having high generating time of high voltage pulse is opened is lower than 0.2mm/sec, the starting probability is improved to 95%.

Abstract: PURPOSE:To measure the change in the electric characteristics of a semiconductor thereby to measure the influence upon the reliability and lifetime for a short time by impressing a backward voltage between the electrodes of the device and by continuing that condition for a longer period than a preset time CONSTITUTION:A transistor 1 is held in a constant temperature bath 2, and a suitable backward voltage is impressed for a preset time between the collector and base of the transistor 1 After the continuation for several ten to hundred hours, the leak current, current amplification and forward drop of the transistor are measured and compared with the values before the tests so that the influences upon the reliablity and lifetime of a semiconductor chip can be judged

Abstract: PURPOSE:To improve the reliability of a measurement by making plural contact pins contact with a wired substrate automatically and by testing whether an element of the desired value is present at the desired position by means of an automatic microprogram processing. CONSTITUTION:The automatic testing device consists of the arithmetic processing part A, test signal part B, changeover part C and unit bed D. The arithmetic processing part A controls the device in accordance with a program. The test signal part B sends both a read value and a decided data to the arithmetic processing part. The changeover part C selects an optimum reference resistance for an element to be measured in the substrate to be measured. The unit bed D supports a unit to be measured.

Abstract: Integrated circuit technology has made possible instruments and applications that were inconceivable on the grounds of cost, size and reliability a decade ago.

Abstract: PURPOSE:To ensure the economization of the device as well as increase the reliability of the circuit network, by securing the shared control for the 1st-kind control station via the 2nd-kind control station and then setting the above sharing via the control of the 3rd-kind control station each for the circuit switching. CONSTITUTION:At the circuit switching time, 1st-kind control station 1 sends the data of the stand-by circuit memorized in its own station to 2nd-kind control station 2 via 1st-kind control line 4. Then control station 2 secures the combined gathering between the stand-by circuit memorized in the self-station and that sent from station 1 to then send it to single 3rd control station 6 along with the circuit switching information which is calculated and memorized previously for the switching in case the fault occurs. Based on the information given, station 6 decides the proper and direct control for station 1 via station 2 in terms of operation of the control system, and then sends the information to decided station 2 via 3rd-kind control line 7. In such constitution, the memory capacity can be reduced for both stations 1 and 2, and the reliability can be increased for the circuit switching since station 6 control the control system only.