TL;DR: This paper proposes P4 as a strawman proposal for how OpenFlow should evolve in the future, and describes how to use P4 to configure a switch to add a new hierarchical label.
Abstract: P4 is a high-level language for programming protocol-independent packet processors. P4 works in conjunction with SDN control protocols like OpenFlow. In its current form, OpenFlow explicitly specifies protocol headers on which it operates. This set has grown from 12 to 41 fields in a few years, increasing the complexity of the specification while still not providing the flexibility to add new headers. In this paper we propose P4 as a strawman proposal for how OpenFlow should evolve in the future. We have three goals: (1) Reconfigurability in the field: Programmers should be able to change the way switches process packets once they are deployed. (2) Protocol independence: Switches should not be tied to any specific network protocols. (3) Target independence: Programmers should be able to describe packet-processing functionality independently of the specifics of the underlying hardware. As an example, we describe how to use P4 to configure a switch to add a new hierarchical label.
TL;DR: This work implements a CNN accelerator on a VC707 FPGA board and compares it to previous approaches, achieving a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.
Abstract: Convolutional neural network (CNN) has been widely employed for image recognition because it can achieve high accuracy by emulating behavior of optic nerves in living creatures. Recently, rapid growth of modern applications based on deep learning algorithms has further improved research and implementations. Especially, various accelerators for deep CNN have been proposed based on FPGA platform because it has advantages of high performance, reconfigurability, and fast development round, etc. Although current FPGA accelerators have demonstrated better performance over generic processors, the accelerator design space has not been well exploited. One critical problem is that the computation throughput may not well match the memory bandwidth provided an FPGA platform. Consequently, existing approaches cannot achieve best performance due to under-utilization of either logic resource or memory bandwidth. At the same time, the increasing complexity and scalability of deep learning applications aggravate this problem. In order to overcome this problem, we propose an analytical design scheme using the roofline model. For any solution of a CNN design, we quantitatively analyze its computing throughput and required memory bandwidth using various optimization techniques, such as loop tiling and transformation. Then, with the help of rooine model, we can identify the solution with best performance and lowest FPGA resource requirement. As a case study, we implement a CNN accelerator on a VC707 FPGA board and compare it to previous approaches. Our implementation achieves a peak performance of 61.62 GFLOPS under 100MHz working frequency, which outperform previous approaches significantly.
TL;DR: In the 21st century, manufacturing companies must possess new types of manufacturing systems that are cost-effective and very responsive to all these market changes as mentioned in this paper, which are the cornerstones of this new manufacturing paradigm.
TL;DR: This paper provides a tutorial introduction of this subject to the reader not working directly in the field but interested in getting an overall introduction of the subject and also to the researcher wishing to get a comprehensive background before working on the subject.
Abstract: Microwave photonic filters are photonic subsystems designed with the aim of carrying equivalent tasks to those of an ordinary microwave filter within a radio frequency (RF) system or link, bringing supplementary advantages inherent to photonics such as low loss, high bandwidth, immunity to electromagnetic interference (EMI), tunability, and reconfigurability. There is an increasing interest in this subject since, on one hand, emerging broadband wireless access networks and standards spanning from universal mobile telecommunications system (UMTS) to fixed access picocellular networks and including wireless local area network (WLAN), World Interoperability for Microwave Access, Inc. (WIMAX), local multipoint distribution service (LMDS), etc., require an increase in capacity by reducing the coverage area. An enabling technology to obtain this objective is based on radio-over-fiber (RoF) systems where signal processing is carried at a central office to where signals are carried from inexpensive remote antenna units (RAUs). On the other hand, microwave photonic filters can find applications in specialized fields such as radar and photonic beamsteering of phased-arrayed antennas, where dynamical reconfiguration is an added value. This paper provides a tutorial introduction of this subject to the reader not working directly in the field but interested in getting an overall introduction of the subject and also to the researcher wishing to get a comprehensive background before working on the subject.
TL;DR: The proposed reprogrammable hologram may be a key in enabling future intelligent devices with reconfigurable and programmable functionalities that may lead to advances in a variety of applications such as microscopy, display, security, data storage, and information processing.
Abstract: Metasurfaces have enabled a plethora of emerging functions within an ultrathin dimension, paving way towards flat and highly integrated photonic devices. Despite the rapid progress in this area, simultaneous realization of reconfigurability, high efficiency, and full control over the phase and amplitude of scattered light is posing a great challenge. Here, we try to tackle this challenge by introducing the concept of a reprogrammable hologram based on 1-bit coding metasurfaces. The state of each unit cell of the coding metasurface can be switched between ‘1’ and ‘0’ by electrically controlling the loaded diodes. Our proof-of-concept experiments show that multiple desired holographic images can be realized in real time with only a single coding metasurface. The proposed reprogrammable hologram may be a key in enabling future intelligent devices with reconfigurable and programmable functionalities that may lead to advances in a variety of applications such as microscopy, display, security, data storage, and information processing. Realizing metasurfaces with reconfigurability, high efficiency, and control over phase and amplitude is a challenge. Here, Li et al. introduce a reprogrammable hologram based on a 1-bit coding metasurface, where the state of each unit cell of the coding metasurface can be switched electrically.