About: RDRAM is a research topic. Over the lifetime, 35 publications have been published within this topic receiving 570 citations. The topic is also known as: Rambus DRAM & RIMM.
TL;DR: Providing three times the memory bandwidth of the 66-MHz SDRAM subsystem, Direct RDRAM modules fit seamlessly into the existing mechanical space and airflow environment of the industry-standard PC chassis.
Abstract: Providing three times the memory bandwidth of the 66-MHz SDRAM subsystem, Direct RDRAM modules fit seamlessly into the existing mechanical space and airflow environment of the industry-standard PC chassis.
TL;DR: The fundamental concepts of these recent high-speed performance memory architectures are discussed to aid in the selection of memories for multimedia applications.
Abstract: In order to meet the requirements for multimedia applications, several approaches to DRAM architecture have emerged. Instead of a single, common memory device, several advanced approaches, such as extended data out (EDO) DRAM, and synchronous DRAM (SDRAM) will each play a major role in the future memory market. Furthermore, advanced interface technologies, such as Rambus RAM (RDRAM), RamLink, and SyncLink are very promising for future-generation memory. Also, application-specific memory, such as cache DRAM (CDRAM), enhanced DRAM (EDRAM), and video DRAM (VRAM) offer unique characteristics to improve performance in particular applications. Since it is beneficial to understand which type of high-speed memory can improve the speed performance of a particular system most effectively, this article discusses the fundamental concepts of these recent high-speed performance memory architectures to aid in the selection of memories for multimedia applications.
TL;DR: It is found that accessing unit-stride streams in cacheline bursts in the natural order of the computation exploits from 44-76% of the peak bandwidth of a memory system composed of a single Direct RDRAM device, and that accessing streams via a streaming mechanism with a simple access ordering scheme can improve performance by factors of 1.18 to 2.25.
Abstract: Processor speeds are increasing rapidly and memory speeds are not keeping up. Streaming computations (such as multimedia or scientific applications) are among those whose performance is most limited by the memory bottleneck. Rambus hopes to bridge the processor/memory performance gap with a recently introduced DRAM that can deliver up to 1.6 Gbytes/sec. We analyze the performance of these interesting new memory devices on the inner loops of streaming computations, both for traditional memory controllers that treat all DRAM transactions as random cacheline accesses, and for controllers augmented with streaming hardware. For our benchmarks, we find that accessing unit-stride streams in cacheline bursts in the natural order of the computation exploits from 44-76% of the peak bandwidth of a memory system composed of a single Direct RDRAM device, and that accessing streams via a streaming mechanism with a simple access ordering scheme can improve performance by factors of 1.18 to 2.25.
TL;DR: By implementing all seven key multimedia functions using a single media processor, Chromatic Research has redefined the multimedia PC and raises the bar on base PC multimedia functionality.
Abstract: By implementing all seven key multimedia functions (MPEG video, 2D graphics, 3D graphics, audio, fax/modem, telephony, and videophone) using a single media processor, Chromatic Research has redefined the multimedia PC. Utilizing a high bandwidth RAMBUS RDRAM for media memory and a VLIW SIMD internal architecture, the Mpact M1 media processor is able to deliver 2 BOPS of sustained integer performance at a price point significantly below alternative discrete hardware implementations. By cooperatively solving multimedia tasks with the host processor, by supporting Win '95 APIs, and by supporting PC legacy needs such as VGA graphics and FM audio, the M1 raises the bar on base PC multimedia functionality.
TL;DR: The operating speed of microprocessors has become faster than 500 MHz, while memory access speed has not been improved accordingly in spite of quadrupled increase in the memory density every three years, requiring memory systems to use a wide data-bus and/or a high-speed I/O interface to increase access speed.
Abstract: The operating speed of microprocessors has become faster than 500 MHz, while memory access speed has not been improved accordingly in spite of quadrupled increase in the memory density every three years. This imbalance requires memory systems to use a wide data-bus and/or a high-speed I/O interface to increase access speed. Increasing access speed with a wide data-bus is studied, but is practically limited by memory pin counts. Alternatively, Rambus DRAM (RDRAM) achieves access speed up to 800 MB/s in a well-controlled printed circuit board (PCB) environment by adopting a high-speed I/O interface. Low cost systems use synchronous DRAM (SDRAM) interface because they cannot afford a high-cost PCB. This system limits memory access speed to the system clock speed, which is commonly less than 100 MHz. Double data rate (DDR) SDRAM, is twice as fast as SDRAM memory access by taking both rising and falling edges of the system clock, while keeping the SDRAM interface. To deal with clock skew, the DDR SDRAM provides an extra strobe signal for the receiving end.