About: Racetrack memory is a research topic. Over the lifetime, 610 publications have been published within this topic receiving 16577 citations. The topic is also known as: domain-wall memory.
TL;DR: The racetrack memory described in this review comprises an array of magnetic nanowires arranged horizontally or vertically on a silicon chip and is an example of the move toward innately three-dimensional microelectronic devices.
Abstract: Recent developments in the controlled movement of domain walls in magnetic nanowires by short pulses of spin-polarized current give promise of a nonvolatile memory device with the high performance and reliability of conventional solid-state memory but at the low cost of conventional magnetic disk drive storage. The racetrack memory described in this review comprises an array of magnetic nanowires arranged horizontally or vertically on a silicon chip. Individual spintronic reading and writing nanodevices are used to modify or read a train of ∼10 to 100 domain walls, which store a series of data bits in each nanowire. This racetrack memory is an example of the move toward innately three-dimensional microelectronic devices.
TL;DR: It is found that the Néel skyrmion moved by the spin-Hall effect is a very promising strategy for technological implementation of the next generation of skyrMion racetrack memories (zero field, high thermal stability, and ultra-dense storage).
Abstract: Magnetic storage based on racetrack memory is very promising for the design of ultra-dense, low-cost and low-power storage technology. Information can be coded in a magnetic region between two domain walls or, as predicted recently, in topological magnetic objects known as skyrmions. Here, we show the technological advantages and limitations of using Bloch and Neel skyrmions manipulated by spin current generated within the ferromagnet or via the spin-Hall effect arising from a non-magnetic heavy metal underlayer. We found that the Neel skyrmion moved by the spin-Hall effect is a very promising strategy for technological implementation of the next generation of skyrmion racetrack memories (zero field, high thermal stability, and ultra-dense storage). We employed micromagnetics reinforced with an analytical formulation of skyrmion dynamics that we developed from the Thiele equation. We identified that the excitation, at high currents, of a breathing mode of the skyrmion limits the maximal velocity of the memory.
TL;DR: Racetrack memory stores digital data in the magnetic domain walls of nanowires to yield information storage devices with high reliability, performance and capacity.
Abstract: Racetrack memory stores digital data in the magnetic domain walls of nanowires. This technology promises to yield information storage devices with high reliability, performance and capacity.
TL;DR: The vertical magnetoresistive random access memory design based on micromagnetic simulation analysis is presented and it is suggested that this memory design has the potential to not only replace the present semiconductor memory devices, such as FLASH, but also the ability to replace DRAM, SRAM, and even disk drives.
Abstract: In this paper, we present the vertical magnetoresistive random access memory (VMRAM) design based on micromagnetic simulation analysis. The design utilizes the vertical giant magnetoresistive effect of the magnetic multilayer. By making the memory element into a ring-shaped magnetic multilayer stack with orthogonal paired word lines, magnetic switching of the memory device becomes very robust. The design also adopts the readback scheme in pseudo spin valve MRAM so that only one transistor is needed for each bit line which can connect hundreds of memory elements, yielding a very high area density. It is estimated that the ultimate area density for the VMRAM is 400 Gbits/in.2. It is suggested that this memory design has the potential to not only replace the present semiconductor memory devices, such as FLASH, but also the potential to replace DRAM, SRAM, and even disk drives.
TL;DR: An effective and simple method to avoid the clogging of skyrmionic bits is demonstrated, which ensures the elimination of skyrsion bits beyond the reading element.
Abstract: Magnetic skyrmions are promising for building next-generation magnetic memories and spintronic devices due to their stability, small size and the extremely low currents needed to move them. In particular, skyrmion-based racetrack memory is attractive for information technology, where skyrmions are used to store information as data bits instead of traditional domain walls. Here we numerically demonstrate the impacts of skyrmion-skyrmion and skyrmion-edge repulsions on the feasibility of skyrmion-based racetrack memory. The reliable and practicable spacing between consecutive skyrmionic bits on the racetrack as well as the ability to adjust it are investigated. Clogging of skyrmionic bits is found at the end of the racetrack, leading to the reduction of skyrmion size. Further, we demonstrate an effective and simple method to avoid the clogging of skyrmionic bits, which ensures the elimination of skyrmionic bits beyond the reading element. Our results give guidance for the design and development of future skyrmion-based racetrack memory.