Abstract: This paper presents a three-phase transformerless cascade pulsewidth-modulation (PWM) static synchronous compensator (STATCOM) intended for installation on industrial and utility power distribution systems. It proposes a control algorithm that devotes itself not only to meeting the demand of reactive power but also to voltage balancing of multiple galvanically isolated and floating dc capacitors. The control algorithm based on a phase-shifted carrier modulation strategy is prominent in having no restriction on the cascade number. Experimental waveforms verify that a 200-V 10-kVA cascade PWM STATCOM with star configuration has the capability of inductive to capacitive (or capacitive to inductive) operation at the rated reactive power of 10 kVA within 20 ms while keeping the nine dc mean voltages controlled and balanced even during the transient state.

Abstract: A new predictive strategy for current control of a three-phase neutral-point-clamped inverter is presented. The algorithm is based on a model of the system. From that model, the behavior of the system is predicted for each possible switching state of the inverter. The state that minimizes a given quality function is selected to be applied during the next sampling interval. Several compositions of are proposed, including terms dedicated to achieve reference tracking, balance in the dc link, and reduction of the switching frequency. In comparison to an established control method, the strategy presents a remarkable performance. The proposed method achieves comparable reference tracking with lower switching frequency per semiconductor and similar transient behavior. The main advantage of the method is that it does not require any kind of linear controller or modulation technique, achieving a different approach to control a power converter.

Abstract: In this paper, three different inverters: conventional pulsewidth modulation (PWM) inverter, dc-dc boosted PWM inverter, and Z-source inverter were investigated and compared for fuel cell vehicle application. Total switching device power, passive components requirement, and constant power speed ratio of each of these inverters were calculated. For purposes of comparison, an example of the total switching device power, requirement of passive components, the constant power speed ratio, and the efficiencies of the different inverters for fuel cell vehicle powered by the same fuel cell were conducted. The comparisons show that the Z-source inverter is very promising in applications when the boost ratio is low (1-2).

Abstract: This work presents a comparison of various maximum power point tracking (MPPT) techniques applied to 1-Phi, single-stage, grid-connected photovoltaic (PV) systems. A representative single-stage grid-connected PV system, based on buck-boost converter topology operating in discontinuous current mode (DCM) with sine-triangle pulse width modulation (SPWM) and feeding sinusoidal power into the grid, is considered for this study. MPPT techniques are compared on the basis of the time taken to reach (track) the MPP, operating point oscillations in the vicinity of MPP and the dependence of the algorithms, if any, on array configuration and parameters. Comparison is also made on the basis of the energy extracted from the PV source during the transient tracking phase. In this context, an energy tracking factor term (E TF ) is introduced and defined. It is observed that all the MPPT schemes studied have their own merits and demerits. The ripple correlation and beta methods offer an overall good combination of desirable features. All the results of this study are presented.

Abstract: An H-bridge circuit is connected to a coil of the vibration motor that is to be driven. A comparator receives Hall signals indicating position information of a rotor of the vibration motor, and converts to an FG signal. A pulse width modulator generates a pulse-modulated pulse signal specifying energization time of the coil of the vibration motor. The pulse width modulator, in a first mode, after commencing start-up of the vibration motor, sets a duty ratio of the pulse signal to 100%, and after that, switches the duty ratio to a predetermined value in accordance with rotational frequency of the motor. In a second mode, the duty ratio of the pulse signal continues to be set to 100%. In a third mode, frequency and the duty ratio of the pulse signal are set based on a control signal of a pulse form inputted from outside. The control signal is used also in switching mode.

Abstract: This paper proposes predictive direct power control (P-DPC), a new control approach where the well-known direct power control is combined with predictive selection of a voltage-vectors' sequence, obtaining both high transient dynamics and a constant-switching frequency. The developed P-DPC version is based on an optimal application of three voltage vectors in a symmetrical way, which is the so-called symmetrical 3 + 3 vectors' sequence. The simulation and experimental results of the P-DPC are compared to standard voltage-oriented control (VOC) strategies in a grid-connected three-phase voltage-source inverter under 400-V 15-kVA operation conditions. The P-DPC improves the transient response and keeps the steady-state harmonic spectrum at the same level as the VOC strategies. Due to its high transient capability and its constant-switching behavior, the P-DPC could become an interesting alternative to standard VOC techniques for grid-connected converters

Abstract: The letter presents an exact small-signal discrete-time model for digitally controlled pulsewidth modulated (PWM) dc-dc converters operating in constant frequency continuous conduction mode (CCM) with a single effective A/D sampling instant per switching period. The model, which is based on well-known approaches to discrete-time modeling and the standard Z-transform, takes into account sampling, modulator effects and delays in the control loop, and is well suited for direct digital design of digital compensators. The letter presents general results valid for any CCM converter with leading or trailing edge PWM. Specific examples, including approximate closed-form expressions for control-to-output transfer functions are given for buck and boost converters. The model is verified in simulation using an independent system identification approach.

Abstract: This paper presents a novel modulation strategy for a neutral-point-clamped converter. This strategy overcomes one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point under some operating conditions. The proposed modulation strategy can completely remove this oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads. The algorithm is based on a carrier-based pulsewidth modulation. Nevertheless, it can generate the maximum output-voltage amplitudes that are attainable under linear modulation, such as space-vector modulation. Furthermore, this technique can be implemented with a very simple algorithm and, hence, can be processed very quickly. The only drawback of this strategy is that the switching frequencies of the devices are one third higher than those of standard sinusoidal pulsewidth modulation. A control loop for balancing the voltages on the dc-link capacitors is also proposed. This balancing strategy is designed, so that it does not further increase the switching frequencies of the devices when it is applied to the converter. The proposed modulation technique is verified by simulation and experiment.

Abstract: Due to the development of new grid codes, power converters' output signal harmonic control is currently becoming extremely important in medium- and high-power applications. By taking this new scenario into account, a new method to generate switching three-level pulsewidth-modulation (PWM) patterns to meet specific grid codes is presented. The proposed method, which is named selective harmonic mitigation PWM , generates switching three-level PWM patterns with high quality from the point of view of harmonic content, avoiding the elimination of some specific harmonics and studying all harmonics and the total harmonic distortion as a global problem by using a general-purpose random-search heuristic algorithm. This fact leads to a drastic reduction or even avoidance of the bulky and costly grid connection tuned filters of power systems. Any harmonic shaping can be considered due to the flexibility of the method. Power devices switching constraints are considered to obtain directly applicable results. As a practical example, limits from one actual grid code have been used to get the experimental results by means of a 150-kVA three-level diode-clamped converter test bench. Comparisons between the proposed technique, optimized PWM and Selective Harmonic Elimination methods have been carried out. The results obtained with this new method greatly improve previous ones.

Abstract: The issue of voltage imbalance remains a challenge for the flying capacitor multilevel converter. The phase-shifted pulsewidth modulation (PS-PWM) method has a certain degree of self-balancing properties. However, the method alone is not sufficient to maintain balanced capacitor voltages in practical applications. The paper proposes a closed-loop modified PS-PWM control method by incorporating a novel balancing algorithm. The algorithm takes advantage of switching redundancies to adjust the switching times of selected switching states and thus maintaining the capacitor voltages balanced without adversely affecting the system's performance. Key techniques of the proposed control method, including selection of switching states, calculation of adjusting times for the selected states, and determination of new switching instants of the modified PS-PWM are described and analyzed. Simulation and experimental results are presented to confirm the feasibility of the proposed method

Abstract: In this paper, an improved deadbeat current control scheme with a novel adaptive self-tuning load model for a three-phase pulsewidth-modulated (PWM) voltage-source inverter is proposed. First, to achieve high-bandwidth current control characteristics, an improved deadbeat current controller with delay compensation is adopted. The compensation method forces the delay elements, which are caused by voltage calculation, PWM, and synchronous frame rotation, to be equivalently placed outside the closed-loop control system. Hence, their effect on the closed-loop stability is eliminated, and the current controller can be designed with a higher bandwidth. Second, to relax the parameter sensitivity issue of the deadbeat controller and to realize a control scheme with reduced sensors, a novel adaptive self-tuning load model is emerged in the control structure. The adaptive model is designed with low computational demand to estimate in real time the load parameters (R,L) and the back-electromotive-force voltage simultaneously. A unified solution to the present nonlinear estimation problem is presented by adopting a parallel observer structure. Furthermore, the adaptive model has the necessary phase advance of the estimated quantities, which compensates for the total system's delay. Comparative evaluation results are presented to demonstrate the validity and effectiveness of the proposed control scheme

Abstract: This paper presents the design of a novel wide output current range dual-mode dc to dc step-down (Buck) switching regulator/converter. The converter can adaptively switch between pulsewidth modulation (PWM) and pulse-frequency modulation (PFM) both with very high conversion efficiency. Under light load condition the converter enters PFM mode. The function of closing internal idle circuits is implemented to save unnecessary switching losses. The converter can be switched to PWM mode when the load current is greater than 100 mA. Soft start operation is designed to eliminate the excess large current at the start up of the regulator. The chip has been fabricated with a TSMC 2P4M 0.35 mum polycide CMOS process. The range of the operation voltage is from 2.7 to 5 V, which is suitable for single-cell lithium-ion battery supply applications. The maximum conversion efficiency is 95% at 50 mA load current. Above 85 % conversion efficiency can be reached for load current from 3 to 460 mA.

Abstract: Integrated switching power supplies with multimode control are gaining popularity in state-of-the-art portable applications like cellular phones, personal digital assistants (PDAs), etc., because of their ability to adapt to various loading conditions and therefore achieve high efficiency over a wide load-current range, which is critical for extended battery life. Constant-frequency, pulsewidth modulated (PWM) switching converters, for instance, have poor light-load efficiencies because of higher switching losses while pulse-frequency modulation (PFM) control in discontinuous-conduction mode (DCM) is more efficient at light loads because the switching frequency and associated switching losses are scaled down with load current. This paper presents the design and integrated circuit prototype results of an 83% power efficient 0.5-V 50-mA CMOS PFM buck (step-down) dc-dc converter with a novel adaptive on-time scheme that generates a 27-mV output ripple voltage from a 1.4- to 4.2-V input supply (battery-compatible range). The output ripple voltage variation and steady-state accuracy of the proposed supply was 5 mV (22-27 mV) and 0.6% whereas its constant on-time counterpart was 45 mV (10-55 mV) and 3.6%, respectively. The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance

Abstract: The phenomenon of dc-capacitor-voltage drift is the main technical drawback of a passive front-end multilevel diode-clamped converter (DCC). This paper formulates and analyzes the dc-capacitor-voltage-drift phenomenon of a passive front-end five-level DCC, which operates based on a sinusoidal pulsewidth-modulation (SPWM) switching strategy. The analysis shows dependence of the voltage drift on the modulation index and the ac-side power factor of the DCC. The analysis concludes that an SPWM strategy, without the use of auxiliary power circuitry, is not able to prevent the voltage-drift phenomenon of a five-level DCC. This paper also proposes a space-vector-modulation (SVM)-based switching strategy that takes advantage of redundant switching vectors of the SVM method to counteract the voltage-drift phenomenon. The limit to the range of operation of a five-level DCC, which is based on the proposed SVM strategy, is also presented. The salient feature of the proposed strategy is that it enables voltage balancing of the dc capacitors with no requirements for additional controls or auxiliary-power circuitry, within the specified range of operation. The performance of a DCC under various operating conditions, based on time-domain simulation studies in the MATLAB/SIMULINK environment, is evaluated. This paper demonstrates capability of the proposed SVM strategy to control and maintain voltage balance of dc capacitors.

Abstract: Modulation of flying capacitor and stacked multicell converters is complicated by the fact that these converters have redundant states that achieve the same phase leg voltage output. Hence, a modulator must use some secondary criteria such as cell voltage balancing to fully define the converter switched state. Alternatively, the modulator can be adapted to directly specify the cell states, such as has been proposed for the harmonically optimal phase disposition (PD) strategy. However the techniques reported to date can lead to uneven distribution of switching transitions between cells, and the synthesis of narrow switched phase leg pulses. This paper presents an improved strategy that decouples the tasks of voltage level selection and switching event distribution. Conventional PD and centered space vector pulsewidth modulation (CSVPWM) strategies are used to define the target voltage level for the converter, and a finite state machine is then used to distribute the transitions to the converter cells in a cyclical fashion. Experimental results for a four-level flying capacitor inverter are presented, verifying that the natural balancing properties of this converter has been preserved, the cell switching utilization is equal and the expected harmonic gains of PD and CSVPWM compared to phase shifted carrier PWM have been achieved

Abstract: Multilevel inverters have emerged as attractive high-power medium-voltage power-conversion systems. They are mainly controlled with high-frequency pulsewidth-modulation methods. This is not suitable for very high-power application due to significant switching losses. This paper presents an adaptive duty-cycle modulation algorithm that reduces the switching frequency to a minimum necessary to fulfill the dynamic requirements of the system. Switching losses are, therefore, strongly reduced. This is achieved by using the slope of the voltage reference to adapt the modulation period to ensure that only one-step change between two voltage levels. Simulation and experimental results are presented for a nine-level cascaded inverter. Voltage waveforms obtained for variable frequencies and amplitudes show similar switching patterns, with a reduced and near-constant number of commutations per cycle, regardless of the reference frequency and amplitude.

Abstract: The objective of the present work is to improve the output waveform of three level inverters used in high-power applications, where the switching frequency is very low. This is achieved by maintaining the synchronization, half-wave symmetry, quarter-wave symmetry, and three-phase symmetry in the pulsewidth modulation (PWM) waveforms. The principles of achieving synchronization and symmetries in terms of space vectors for three level inverters are presented. A novel synchronized space vector pulsewidth modulation (SVPWM) algorithms is proposed and verified experimentally. The experimental waveforms of the inverter output voltage and motor no load current for different operating conditions of the drive are presented. The performance measure in terms of the weighted total harmonic distortion (THD) of the line voltage is computed for the linear modulation region of the drive for the proposed algorithm and compared with that of synchronized SVPWM and synchronized sine-triangle pulsewidth modulation (SPWM) technique. The comparative results show that consideration of synchronization and symmetry results in improved THD. Another significant feature of the proposed algorithm is that the symmetry and synchronization leads to self-balancing of the direct current (dc) bus capacitor voltages over every one third cycle of the fundamental

Abstract: In recent years, active power filters have been widely studied. The research has mainly concentrated on voltage-source active filters, but some attention has also been paid to an alternative-to current-source active filters. Since voltage-source pulsewidth modulation (PWM) technology is widely used in industrial applications, this has also been more common in active filter use. In addition, current-source technology has been said to have drawbacks compared to voltage-source systems, such as high on-state losses in the PWM bridge and inefficient inductive energy storage element on the dc side of the bridge. In the paper, the two active filter topologies are compared. First, the main circuits and space-vector modulation techniques used are studied and the digital control systems are presented. The filtering performances of the systems with different kinds of nonlinear load are examined and finally the power losses of the active filters are studied. The comparison is based on measurements with the prototypes built. The results clearly show the properties of the active filters examined. In addition, the results prove that current-source active filters also offer a considerable choice for harmonic filtering

Abstract: This paper proposes a novel control scheme of single-phase-to-three-phase pulsewidth-modulation (PWM) converters for low-power three-phase induction motor drives, where a single-phase half-bridge PWM rectifier and a two-leg inverter are used. With this converter topology, the number of switching devices is reduced to six from ten in the case of full-bridge rectifier and three-leg inverter systems. In addition, the source voltage sensor is eliminated with a state observer, which controls the deviation between the model current and the system current to be zero. A simple scalar voltage modulation method is used for a two-leg inverter, and a new technique to eliminate the effect of the dc-link voltage ripple on the inverter output current is proposed. Although the converter topology itself is of lower cost than the conventional one, it retains the same functions such as sinusoidal input current, unity power factor, dc-link voltage control, bidirectional power flow, and variable-voltage and variable-frequency output voltage. The experimental results for the V/f control of 3-hp induction motor drives controlled by a digital signal processor TMS320C31 chip have verified the effectiveness of the proposed scheme

Abstract: This paper presents the careful integration of a newly proposed Z-source topological concept to the basic neutral-point-clamped (NPC) inverter topology for designing a three-level inverter with both voltage-buck and voltage-boost capabilities. The designed Z-source NPC inverter uses two unique X-shaped inductance-capacitance (LC) impedance networks that are connected between two isolated dc input power sources and its inverter circuitry for boosting its AC output voltage. Through the design of an appropriate pulsewidth-modulation (PWM) algorithm, the two impedance networks can be short-circuited sequentially (without shooting through the inverter full DC link) for implementing the ldquonearest-three-vectorrdquo modulation principle with minimized harmonic distortion and device commutations per half carrier cycle while performing voltage boosting. With only a slight modification to the inverter PWM algorithm and by short-circuiting the two impedance networks simultaneously, the designed NPC inverter, with no requirement for deadtime delay, can also be operated with a completely eliminated common-mode voltage. Implementation wise, a detailed vectorial analysis interestingly shows that the same generic set of carrier-based modulation expressions can be used for controlling the -source two-level inverter and NPC inverter with and without reduced common-mode switching. All findings presented in this paper have been confirmed in simulation and experimentally using an implemented laboratory prototype.

Abstract: This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.

Abstract: Control structures and strategies have a critical influence on a power electronic converter's behavior during disturbances. Most of the previous works in the field of pulsewidth modulation voltage-source converter (VSC) operation under unbalanced conditions propose dual vector controllers with dc bus voltage optimization strategies, which have been proven to be well adapted for rectifier applications. In this paper, two major contributions are made. On the one hand, a new optimized operation strategy based on exchanged power maximization is proposed for vector control structures, which permits the extension of optimized operation to other VSC applications (e.g., flexible alternating current transmission system and distributed generation interfaces). On the other hand, a scalar control structure is proposed based on resonant controllers, together with three adapted optimized operation strategies, namely: 1) dc bus voltage optimization; 2) power exchange maximization; and 3) a hybrid strategy (an intermediary mode between the other two strategies). Their main advantage is their simplicity and the lack of real-time symmetrical component extraction techniques. This scalar controller and the proposed optimized operation strategies are compared to conventional vector controllers. It is proven through experimental analysis that the proposed scalar controller offers very good performances with simpler structures and bigger flexibility in terms of operation modes.

Abstract: In this paper, a simple power-control scheme for a constant-frequency class-D inverter with variable duty cycle at constant frequency is proposed. It is more suitable and acceptable for high-frequency induction-heating (IH) jar applications. The proposed control scheme has the advantages of not only wide power-regulation range but also ease of output-power control. In addition, it can achieve stable and efficient zero-voltage switching in the whole load range. The control principles of the proposed method are described in detail, and the validity is verified through the simulated and experimental results on the 42.8-kHz insulated gate bipolar transistor for an IH rated on 1.6 kW with constant-frequency variable power

Abstract: With the rapid development of silicon carbide (SiC) material quality, SiC power devices are gaining tremendous attentions in power electronics. In this paper, a SiC device based motor drive system is performed to provide a quantitative estimate of the system improvement. Two 60 kW motor drive systems based on SiC MOSFET/Schottky diode and Si IGBTs are designed. The power losses of the two inverters with sinusoidal pulse width modulation (SPWM) control are calculated analytically. By comparing the efficiencies, sizes and temperatures of the two designed systems, SiC device shows the superior advantages of smaller loss, better efficiency and smaller size in the same motor drive application.

Abstract: Cascaded H-bridge multilevel inverters are commonly controlled using multicarrier Phase-Shifted PWM, since it allows an even power distribution among the converter power cells, which can lead to lower harmonic distortion in the input current if an adequate transformer is used. However it is known that other multicarrier methods, like Phase Disposition PWM (PD- PWM) have better output voltage quality with lower distortion. Nevertheless, when used with cascaded inverters, this method produces uneven usage of the converter cells, that disables the harmonic cancelations at the transformer input. This paper presents a modified PD-PWM technique, that combines the benefits of both modulation methods, achieving good output voltage and input current quality.

Abstract: This paper presents a new pulsewidth modulation (PWM) for the complete control of the neutral-point voltage in the three-level three-phase neutral-point-clamped (NPC) direct current-alternating current (dc-ac) converter. The balancing of the neutral-point voltage is achieved over the full range of converter output voltages and for all load power factors with the minimum output voltage distortion at around the switching frequency. The simple phase duty-ratio expressions in d-q-0 coordinates that define this modulation are presented. The performance of this modulation approach and its benefits over other previously proposed solutions are verified through simulation and experiments.

Abstract: A three-phase three-switch buck-type pulsewidth modulation rectifier is designed for telecom applications in this paper. The rectifier features a constant 400-V output voltage and 5-kW output power at the three-phase 400-V mains. The principle of operation and the calculation of the relative on-times of the power transistors are described. Based on analytical relationships the stresses of the active and passive components are determined and the accuracy of the given calculations is verified by digital simulations. Exemplarily, a 5-kW power converter is then designed based on the analytical expressions and on switching loss measurements from a hardware prototype constructed with insulated gate bipolar transistor/diode power modules. The loss distribution of the components, the total efficiency, and the junction temperatures of the semiconductors are then evaluated in dependency on the operating point. Finally, the trade-off between the selected switching frequency and the admissible power range for the realized design is shown and a total efficiency of 95.0% is measured on the hardware prototype, where an excellent agreement with the theoretically evaluated efficiency is shown

Abstract: Multilevel inverters can reduce the common mode voltage generated. Schemes have been reported for multilevel inverters that reduce the common mode voltage. However, most of the schemes result in reduced modulation depth, high switching losses, and high harmonic distortion. This paper proposes a space-vector modulation scheme to reduce common mode voltage for cascaded multilevel inverters. The proposed scheme can increase the voltage range of operation by about 17% and can produce lower total harmonic distortion than the previously proposed schemes. The scheme is explained for five-level inverter. The scheme can be easily extended to a n-level inverter. Both experimental and simulation results are provided.

Abstract: This paper proposes a technique to compensate the effects of dead time in sinusoidal pulsewidth-modulated voltage-source inverters. The compensation is implemented by adjusting the switching frequency to avoid unfeasible pulsewidths of the gating signals, as well as to minimize the total harmonic distortion of the inverter output voltage. The technique can be used at any switching frequency, but the best results are obtained in the high-frequency range. The experimental results of the proposed technique that is applied in a three-phase induction motor drive system are presented.