Planar process

Abstract: The race on the Complementary Metal-Oxide-Semiconductor (CMOS) More Moore integration scale has brought to light several major limitations for efficient planar process integration starting with the 40 nm technology node. The transistor channel was more and more difficult to control in terms of electrostatics, and many process engineering methods (such as, for example, Silicon strain) were used to provide transistors with good carrier speed and decent electrical characteristics. Starting from the 28-nm node, the obvious solution for transistors with increased electrical performances was the use of fully depleted devices. Two integration methods have been identified by the semiconductor industry for these fully depleted devices: Fully Depleted Silicon on Insulator (FD-SOI) CMOS and Fin-FET CMOS devices. While the fundamental carrier semiconductor equations are similar, the process integration is very different. This article focuses on planar FDSOI CMOS technology features as integrated by STMicroelectronics in the 28-nm node [1], [2], and its specificities for analog, radio frequency (RF), millimeter wave (mmW), and mixed signal systemon-chip (SoC) integration.

Abstract: A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

Abstract: Based on the surface-gate and buried-gate structures, a buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed. An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented. Using this structure, it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate. The experimental results demonstrate that this structure is desirable for application in power SIDs. Its advantages are high breakdown voltage and blocking gain.