Topic
Physical verification
About: Physical verification is a research topic. Over the lifetime, 473 publications have been published within this topic receiving 7073 citations.
Papers published on a yearly basis
Papers
1 May 2000
TL;DR: This book discusses Behavioral versus RTL Thinking, high-level modeling, and more about the role of Verification in VHDL vs. Verilog.
Abstract: About the Cover. Foreword. Preface. Why This Book Is Important. What This Book Is About. What Prior Knowledge You Should Have. Reading Paths. Choosing a Language: VHDL vs. Verilog. Hardware Verification Languages. And the Winner is... For More Information. Acknowledgements. 1: What is Verification? What is a Testbench? The Importance of Verification. Reconvergence Model. The Human Factor. What Is Being Verified? Functional Verification Approaches. Testing Versus Verification. Design and Verification Reuse. The Cost of Verification. Summary. 2: Verification Tools. Linting Tools. Simulators. Verification Intellectual Property. Waveform Viewers. Code Coverage. Functional Coverage. Verification Languages. Assertions. Revision Control. Issue Tracking. Metrics. Summary. 3: The Verification Plan. The Role of the Verification Plan. Levels of Verification. Verification Strategies. From Specification to Features. Directed Testbenches Approach. Coverage-Driven Random-Based Approach. Summary. 4: High-Level Modeling. Behavioral versus RTL Thinking. You Gotta Have Style! Structure of Behavioral Code. Data Abstraction. Object-Oriented Programming. Aspect-Oriented Programming. The Parallel Simulation Engine. Race Conditions. Verilog Portability Issues. Summary. 5: Stimulus and Response. Reference Signals. Simple Stimulus. Simple Output. Complex Stimulus. Bus-Functional Models. Response Monitors. Transaction-Level Interface. Summary. 6: Architecting Testbenches. Test Harness. VHDL Test Harness. Design Configuration. Self-Checking Testbenches. Directed Stimulus. Random Stimulus. Summary. 7: Simulation Management. Behavioral Models. Pass or Fail? Managing Simulations. Regression. Summary. Appendix A: Coding Guidelines. Directory Structure. General CodingGuidelines. Naming Guidelines. HDL Coding Guidelines. Appendix B: Glossary. Afterwords. Index.
427 citations
Patent•
22 Dec 2000TL;DR: In this paper, a hierarchical database is used to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion).
Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.
323 citations
Patent•
30 Sep 1997
TL;DR: In this article, a method and system for performing layout verification on an integrated circuit (IC) design using reusable sub-designs is presented, where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design.
Abstract: A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.
293 citations
TL;DR: This paper reviews the standard definitions of verification and validation in the context of engineering design and progresses to provide a coherent analysis and classification of these activities from preliminary design, to design in the digital domain and the physical verification and validate of products and processes.
282 citations
Patent•
1 Aug 2007
TL;DR: In this article, a system and a method of maximizing the manufacturing yield of integrated circuit (IC) design using IC fabrication process simulation driven layout optimization is described, where an IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools.
Abstract: A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.
221 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2021 | 6 |
| 2020 | 11 |
| 2019 | 16 |
| 2018 | 12 |
| 2017 | 15 |
| 2016 | 23 |