Abstract: This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

Abstract: The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

Abstract: In this paper, we propose an adaptive PI (proportional-integral) rate controller for the AQM (active queue management) router that would support best-effort traffic in the Internet Unlike most window-based controllers, our rate-based controller design is derived from the classical control theory and it would allow the users to achieve good stability robustness of the AQM control system by specifying a proper phase margin We also make our controller adaptive by selecting a simple heuristic parameter to monitor the network environment real-time so that the controller would self-tune only when a dramatic change of the network traffic has drifted the monitoring parameter outside its specified interval Located in the router, the adaptive PI rate controller calculates desirable source window sizes (ie, source sending rates) based on the instantaneous queue length of the buffer and advertises it to the sources Our simulations demonstrate that our AQM control system can adapt very well to sudden changes in network environment, thus providing the network with good transient behavior By making the source sending rate relatively smooth, our adaptive PI rate controller becomes quite suitable for streaming media traffic control in the Internet

Abstract: This paper addresses auto-tuning of digital controllers for point-of-load (POL) switching converters with wide range of capacitive loads. Two auto-tuning methods are considered with particular attention given to robustness and feasibility. The first method is derived from the well known relay-feedback autotuning technique, where specific frequencies are excited to gain information on the power stage. In the second, system-identification based method, compensator parameters are computed based on on-line identification of the power stage frequency response. The tuning techniques proposed in this paper have been specifically developed to handle wide capacitance and ESR range, and important extensions of the basic algorithms are implemented in order to face practical issues such as limit cycling conditions, output voltage tolerance specification, closed-loop bandwidth maximization and phase margin constraints. Simulation and experimental results on a 12-to-1.5 V, 9 A, 200 kHz POL converter are provided to show the effectiveness and to compare the considered techniques.

Abstract: A time-domain design method for digital controller of PWM DC-DC converters that was developed, tested by simulations and verified experimentally. The proposed approach is based on the fact that the closed-loop response of a digitally controlled system is largely determined by the first few samples of the compensator. This concept is used to fit a digital PID template to the desired response. The proposed controller design method is carried out in the time domain and thus, bypasses errors related to continuous to discrete domain transformation and discretization. Digital PID controllers for a Buck and Boost type converters were implemented experimentally on a TMS320LF2407 DSP core. The measured closed-loop attributes were 3.5KHz bandwidth and phase margin of 40° for the Buck converter, and 1.6 KHz and 40° for the Boost. Good agreement was found between the design goals and the experimentally determined response.

Abstract: This paper describes an autopilot design of tilt-rotor UAV, which is being developed by KARI as a Smart UAV Development Program in Korea, using particle swarm optimization (PSO) method. The tilt-rotor UAV considered in this paper holds five control modes in the stability and control augmentation system (SCAS) depending on flight mode. Flight control systems designed via the classical approach have been performed in such a way that yields linear models about several trim flight conditions, designing linear controllers for each condition, and integrating these design points with a gain scheduling scheme. However, it is very tedious and time-consuming to design an autopilot of a tilt-rotor UAV which represents various dynamic characteristics, nonlinearity, and uncertainty via classical control technique, because there are many design points and operating conditions throughout the flight envelope. To solve this problem, an automatic tool for control system design using PSO method is developed and applied to autopilot design of tilt-rotor UAV. The desired output of control system is chosen to satisfy the control system requirement. Gain margin and phase margin of control system are additionally considered as a penalty term in the objective function. The designed control system guarantees the satisfaction of the control system requirement ensuring a sufficient stability margin of the control system. Also, the gain scheduling scenario and SCAS switching logic of each control mode are successfully designed. Fully nonlinear 6-DOF simulation for an automatic landing scenario is performed to verify the performance of autopilot system of tilt-rotor UAV. The results from the nonlinear simulation show good control performance of the tilt-rotor UAV.

Abstract: A simple method of designing the controllers for a modified form of Smith predictor is proposed for integrating and double integrating processes with time delay. The modified Smith predictor has two controllers, namely, a set point tracking controller and a load disturbance rejection controller for obtaining good set point tracking and load disturbance rejection, respectively. The set point tracking controller is designed using the classical direct synthesis method based on the process model without considering the time delay. The disturbance rejection controller is considered as a proportional-derivative (PD) controller and is designed using optimal gain and phase margin approaches. Set point weighting is considered for reducing undesirable overshoots and settling times in the modified Smith predictor. Guidelines are provided for selection of the desired closed loop tuning parameter in the direct synthesis method and the set point weighting parameter. The method gives significant load disturbance rejection performances. Illustrative examples are considered to show the performances of the proposed method. A significant improvement in control performance is obtained when compared to recently reported methods.

Abstract: A adaptive pole and zero and Pole-Zero Cancellation Control Low Drop-Out (LDO) regulator is provided, which includes a regulation unit, an error amplifier, a Miller Effect Pole control unit, a Pole Zero Cancellation delay unit, and a feedback network. Pole and Zero could be adaptive regulated depend on various loads and maintain stably in a perfect phase margin.

Abstract: We used a computational model of rhythmic movement to analyze how the connectivity of sensory feedback affects the tuning of a closed-loop neuromechanical system to the mechanical resonant frequency (ωr). Our model includes a Matsuoka half-center oscillator for a central pattern generator (CPG) and a linear, one-degree-of-freedom system for a mechanical component. Using both an open-loop frequency response analysis and closed-loop simulations, we compared resonance tuning with four different feedback configurations as the mechanical resonant frequency, feedback gain, and mechanical damping varied. The feedback configurations consisted of two negative and two positive feedback connectivity schemes. We found that with negative feedback, resonance tuning predominantly occurred when ωr was higher than the CPG’s endogenous frequency (ωCPG). In contrast, with the two positive feedback configurations, resonance tuning only occurred if ωr was lower than ωCPG. Moreover, the differences in resonance tuning between the two positive (negative) feedback configurations increased with increasing feedback gain and with decreasing mechanical damping. Our results indicate that resonance tuning can be achieved with positive feedback. Furthermore, we have shown that the feedback configuration affects the parameter space over which the endogenous frequency of the CPG or resonant frequency the mechanical dynamics dominates the frequency of a rhythmic movement.

Abstract: A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

Abstract: An autotuning technique of voltage-mode regulators for digitally controlled dc-dc converters, which is based on model reference approach, is proposed. The system is excited by a frequency component which equals the desired control bandwidth. The difference between the output of real system and the one of the reference model is used to set regulator parameters in order to obtain desired gain and phase margin at the crossover frequency. The procedure is firstly described for two-parameters controllers (proportional-integral (PI) or proportional derivative (PD) controller) and then extended to more general PID regulators. The latter is obtained either injecting an additional frequency component, or, alternatively, using a single frequency signal in a two step procedure. The proposed solution has the advantage of simplicity, good precision in presence of sampling noise, independence on the converter topology, and small signal processing requirement. Experimental investigation has been performed on a synchronous buck converter, and both simulation and experimental results confirm the effectiveness of the proposed solution.

Abstract: A multi-objective genetic algorithm approach is proposed to design tolerance controllers for uncertain interval systems. Given a set of specifications in terms of acceptability ranges of gain margin (GM) and phase margin (PM), the design objective is to evolutionarily derive controllers such that closed-loop stability and desired dynamic performance are guaranteed. On the basis of extremal design philosophy, the design problem is first formulated as constrained optimisation problems based on deviation between the desired and extremal GM/PM of the resulting loop-transfer function, and subsequently optimised via the proposed genetic algorithm. To ensure robust stability of the closed-loop system, root locations associated with the generalised Kharitonov segment polynomials will be used to establish a constraints handling mechanism, on the basis of which fitness functions can be constructed for effective evaluation of chromosomes in the current population. Because of the cost functions that adopt the concept of centrality, evolution is directed towards derivation of Pareto-optimal solutions of the tolerance controllers with better centrality and limited spreading along the desired region of acceptability, resulting in more consistent system performances and improved robustness of the closed-loop system.

Abstract: HIGH GAIN LOW POWER OPERATIONAL AMPLIFIER DESIGN AND COMPENSATION TECHNIQUES Lisha Li Department of Electrical and Computer Engineering Doctor of Philosophy This dissertation discusses and compares the existing compensation methods for operational amplifiers It explores a method to stabilize the op amps without sacrificing bandwidth to the same degree that commonly used methods do A creative design methodology combining intuition, mathematical analysis, and mixed level simulation is explored for the new compensation scheme The mixed level approach, associating system level simulation for most circuits along with device level simulation for some critical analog circuit paths, is presented to verify the behavior of new design concepts in an effective way This approach also provides sufficient accuracy to predict the circuit performance realistically The new feedforward compensation method overcomes the serious drawback of the widely used pole splitting method, which greatly narrows the bandwidth It can improve the phase margin as well as optimize the bandwidth of the op amp The proposed feedforward compensation method can be easily applied to the popular two gain stage op amp architectures with very little alteration MOS devices are used in the weak inversion region or the subthreshold inversion region to minimize dc source power A feasible configuration for high gain, low power op amp design utilizing subthreshold operation along with active operation is proposed This op amp uses composite cascode connections for the differential input stage, a common source second stage, and a current mirror A prototype of the op amp was fabricated in a 025 μm CMOS process The proposed op amp produces an open loop gain above one million with low power consumption around 110 μW and shows a favorable slew rate and GBW product compared to other amplifiers driving large capacitive loads In addition, the composite cascode amplifier requires a compensation capacitor of only 35 pF which allows a very small op amp cell This design is intended for applications where simplicity of layout, small cell size, and low power are important The open loop gain of this design is comparable to bipolar op amps and exceeds all known reported CMOS designs using the classic Widlar architecture The fabricated op amp test results show that the BSIM3 model in CADENCE Spectre Spice Simulation matches closely to the experimental results in spite of the low current weak inversion operation of the composite cascode output device and thus provide confidence in the simulation for other similar designs While facing the challenge of measuring the op amp open loop characteristics at decreased power supply voltages, a few viable techniques were developed to measure the op amp open loop parameters using typically available bench test equipment

Abstract: A low-dropout voltage (LDO) regulator that creates a zero in the open loop gain using a relatively small-sized current control element to divert part of the supplied load current through a “zero” resistor before adding it to the output load. The main part of the output load is passed through a relatively large second current control element. A control signal generated by an error amplifier (e.g., an op-amp) is used to control the small current control element, but is passed through a boost zero compensating resistor before being applied to the large current control element. The voltage signal developed across the “zero” resistor mimics the magnitude and phase of a zero in the loop. This voltage signal is added to the loop gain by, for instance, using a bypass capacitor, and the resulting feedback signal is supplied to the error amplifier.

Abstract: This paper presents the design of a two-stage pseudo-differential operational transconductance amplifier (OTA). The circuit was designed in a standard 0.18 mum, 0.5 V VT digital CMOS process. An improved bulk-mode common-mode feedback (CMFB) circuit has been designed which does not load the OTA compared to previous design (Chatterjee, 2004). A self cascode load structure and partial positive feedback provide higher gain. The bulk terminals of all transistors have been biased to lower their Vt and maximize signal swing. The OTA operates at a supply voltage of 0.5 V and consumes only 28 muW of power. Rail-to-rail input is made possible by using the transistor's bulk terminal as the input. For a load of 20 pF the OTA has a simulated DC gain of 65 dB, a gain-bandwidth product of 550 kHz, and a phase margin of 500.

Abstract: The invention discloses double ring low voltage difference linear voltage regulator circuit. It includes error amplifier, secondary amplifier, power tube, compensating unit, output sampling network, load capacitance and load circuit, feed-forward amplifier, pull-up driving tube, pull-down driving tube, and sampling tube. It includes two loop circuits that the main one includes the error amplifier, secondary amplifier, pull-up driving tube, power tube, and output sampling network which form negative feedback loop to stably output voltage VOUT; the additional one includes feed-forward amplifier, sampling tube, pull-down driving tube, and power tube which refer to output voltage, form feed back loop to dynamically compensate circuit and further stably output voltage VOUT, and refer to load current, form positive feedback loop to increase load step change for the response circuit. The invention can supply better transient response, periphery circuit selecting, and phase margin for the circuit.

Abstract: An optimal tuning method of PID controller based on gain margin and phase margin is proposed in this paper.The stability region of the controller parameters,which satisfies the required gain margin and phase margin,is first determined on the basis of the improved D-partition approach.Then,in the resultant stability region,the optimal control parameters are found in terms of the objective function related to maximal sensitivity function,overshoot and settling time.Simulation results also demonstrate that,the proposed tuning method ensures that the closed-loop system has strong robustness,good setpoint tracking performance and disturbance rejection performance.It is appropriate not only for stable plants with time delay but also for unstable time-delayed processes.

Abstract: This paper proposes an LCL-filter-based hybrid active power filter for harmonic mitigation of a 10/0.4kV residential distribution system. By using C-LCL-filter based topology, better switching ripples attenuation is achieved, and the phase margin of the power stage at higher frequency is significantly improved. Adaptive linear neural network (ADALINE) is applied for individual harmonic component extraction and the estimated signals are used for selective harmonic elimination (SHE) purposes. A robust deadbeat current control law is derived based on the low frequency model of the presented topology. Owing to the ADALINE based SHE strategy, the controller bandwidth requirement is noticeably diminished thus the stability of whole system is ensured. The feasibility and effectiveness of the proposed system have been substantially confirmed by the laboratory experiments and field tests.

Abstract: A methodology for the systematic design of a programmable operational amplifier (opamp) is described. With this methodology, the opamp is programmable concerning noise and power consumption while keeping the stability for the whole operation range with a constant phase margin of phi res =70deg. The theoretical model is developed with the help of the transfer characteristics of the opamp determining the degrees of freedom. Experimental results for a 0.35-mum CMOS opamp show either ultra low-noise of 2 nV/radicHz or low-power consumption of 140 muW while keeping the opamp stable over the whole range of programmability

Abstract: Nowadays, piezoelectric transformers (PT) are a good alternative to substitute magnetic materials in AC/DC and DC-DC converters. They have high isolation voltage and operate at higher frequencies than magnetics, with lower losses. However, their optimum operating frequency exhibits a strong dependence on different parameters, such as temperature, load, or even voltage level applied. This is usually an inconvenience, because this drift affects PT gain and efficiency, which can vary enormously within a few hundred of hertz. On the other hand, not only is it necessary to ensure the PT is driven at the proper frequency - in terms of gain and efficiency, including zero voltage switching in the power stage - output voltage must also be regulated. In this paper, two simple feedback loops are implemented in a PT-based DC-DC converter. One of them adjusts the switching frequency to obtain the best gain and efficiency. The other one performs the output voltage regulation.

Abstract: In this paper, a novel structure of linear-in-dB gain control is introduced Based on this structure, a wideband variable gain amplifier has been designed and implemented in TSMC 018-mum RF CMOS process On-chip measured results show a good linear-in-dB gain control characteristic with 128 dB dynamic gain range of -33~95 dB It can operate in the frequency range of 43~2330 MHz and consumes 162 mW at 18 V supply The noise figure is 62 dB at maximum gain and the input P1dB at minimum gain is -9 dBm

Abstract: An automatic gain control unit controls the gain applied to an input signal produced by a microphone subject to ambient noise. The automatic gain control circuit continually monitors the signal level of said input signal. A first gain control circuit decreases the gain applied to the input signal in increments of a first size when the input signal exceeds a first predetermined level. A second gain control circuit increases the gain applied to said input signal in increments of a smaller size when the input signal falls below a second predetermined level and in response to the presence of a speech present signal. The second predetermined level is less than said first predetermined level. In one embodiment, the first gain control circuit controls the analog gain of a codec and the second gain control circuit controls the digital gain of the codec.

Abstract: The authors present a simple configuration of a gain-clamped semiconductor optical amplifier (GC-SOA) based on automatic intensity control of a feedback light generated by amplified spontaneous emission, using a narrow bandwidth thin-film-tunable filter. Experimental results show that the proposed amplifier has good gain clamping characteristics and the feedback light dramatically reduces steady and transient gain variations. The feedback light operates satisfactorily with the channel's add-drop frequency up to 20.9 kHz. We also examined the performance of the GC-SOA by employing the feedback light at different wavelengths.

Abstract: When an optical signal that is a wide dynamic range and different in level depending on burst signals is input as in a GPON system, a preamplifier can stably control the gain within a short preamble. The gain changeover of the preamplifier is controlled by the aid of timing information that is extracted from a data signal as data count number, to change over the gain at a high speed and with high precision. A level detector, a preamble recovery, a counter, and a control circuit are disposed within the preamplifier in addition to a TIA main body. In order to suppress the band deterioration or the phase margin reduction which are attributable to the gain changeover, there is provided a bias terminal for conducting a current injection and a current drawing with respect to the signal amplification transistor of the TIA main body.

Abstract: Various example embodiments are disclosed. According to one example embodiment, a high bandwidth, fine granularity variable gain amplifier (“VGA”) may comprise an attenuator, a gain block and a gain adjustment control. The attenuator may comprise at least one pair of attenuator differential input nodes and at least one pair of attenuator differential output nodes. The gain block may comprise at least one pair of gain block differential input nodes coupled to the at least one pair of attenuator differential output nodes and at least one pair of gain block differential output nodes. The gain adjustment control may be configured to adjust a gain of the gain block.

Abstract: A phase/frequency estimator-based phase locked loop (PFE-PLL) may be use to obtain a phase and frequency estimation by using an algebraic summer, a gain block and a (co)sine waveform generator. The apparatus and methods of the present invention may provide the phase estimation of an input signal from which a frequency of the signal is estimated by a derivative function. Unlike conventional phase lock loop systems, which may use a multiplier to perform complex calculations on an input and a feedback signal to develop a demodulated voltage output, the present invention may use a simple algebraic summer to provide an error signal and output a phase and a frequency estimation of the input signal.

Abstract: An adaptive current control circuit for reduced power consumption and minimized gain shift in a variable gain amplifier. An automatic gain control circuit provides gain control voltages in response to a gain control signal. The gain control voltages are used by the variable gain amplifier to set the gain of the output signal for wireless transmit operations. The adaptive current control circuit receives the same gain control voltages for reducing current to the variable gain amplifier during low gain operation, while providing higher currents during high gain operation. The current that is provided is a hybrid mix of proportional to absolute temperature (PTAT) current and complementary to absolute temperature (CTAT) current for minimizing temperature effects on the gain. The ratio of PTAT current and CTAT current is adjustable for specific temperature ranges to further minimize temperature effects on the gain.