Abstract: In industrial practice, controller designs are usually performed based on an approximate model. The parameters of the physical systems can vary with operating conditions and time. Therefore it is essential to design a control system that shows a robust performance in the case of the aforementioned situations. Gain and phase margins are well-known measures for maintaining the robustness of a control system. There are many publications considering controller designs for stable processes based on gain and phase-margin specifications. However, for integrating processes, controller designs with user-specified gain and phase margins are very rare. A new two-degree-of-freedom internal model control structure is presented with simple tuning rules to design and tune PD controllers for integrating processes with a dead time to meet specified gain and phase margins. Simulation examples illustrate that the proposed design method can give better closed-loop system performance than existing design methods based on user-specified gain and phase margins. Simulation results for an assumed perturbation in the process parameters are also given to illustrate the robustness of the proposed controller structure and design method.

Abstract: For the first time, the fractional order disturbance observer (FO-DOB) is proposed for vibration suppression applications such as hard disk drive servo control. It has been discovered in a recently published US patent application (US20010036026) that there is a tradeoff between phase margin loss and strength of the low frequency vibration suppression. Given the required cutoff frequency of the low pass filter, also known as the Q-filter, it turns out that the relative degree of the Q-filter is the major tuning knob for this tradeoff. The solution in US20010036026 was based on an integer order Q-filter with a variable relative degree. This actually motivated the use of a fractional order Q-filter. The fractional order disturbance observer is based on the fractional order Q-filter. The implementation issue is also discussed. The nice point of this paper is that the traditional DOB is extended to the fractional order DOB with the advantage that the FO-DOB design is now no longer conservative nor aggressive, i.e., given the cutoff frequency and the desired phase margin, we can uniquely determine the fractional order of the low pass filter.

Abstract: This paper presents a method of predicting the outer loop gain of dc-dc converters when there is a general (nonresistive) impedance as a load. Based on this prediction, it is possible to then derive a corresponding phase margin, gain margin and bandwidth in order to define a dc-dc converter's stable operating area. Two applications of the method are presented for performance prediction in: 1) dc-dc converters with additional capacitors placed across their load; 2) source converters in a distributed power system. In both applications, the theoretical predictions match closely to the experimental data.

Abstract: The present application describes a frequency compensation scheme for a linear voltage regulator circuit, or its special case, a low-drop out voltage regulator (LDO). According to one embodiment, the frequency compensation scheme includes two circuits, an inner loop compensation circuit (240), and a circuit (245) at the output in parallel with one of the resistors of the output voltage divider (235). These two compensation elements (240, 245) are not interdependent and may be adjusted separately to provide more optimal frequency compensation. Advantages include smaller compensation circuit elements, die or board area savings, better phase margin over process technology variations and operating conditions, and ease of design adjustment.

Abstract: In industrial practice, controller designs are performed based on an approximate model of the actual process. It is essential to design a control system which will exhibit a robust performance because the physical systems can vary with operating conditions and time. Gain and phase margins are well known parameters for evaluating the robustness of a control system. This paper presents a tuning algorithm to design and tune PI controllers for stable processes with a small dead time while meeting specified gain and phase margins. Simulation examples are given to demonstrate that the proposed design method can result, in a closed-loop system, in better performances than existing design methods which are also based on user-specified gain and phase margins.

Abstract: In accordance with the teachings described herein, systems and methods are provided for a precision adaptive equalizer. A variable gain equalizer may be used to apply a variable gain to an input signal to generate an equalized output signal. A phase and pattern detector circuit may be coupled in a feedback loop with the variable gain equalizer. The phase and pattern detector circuit may be used to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error. The phase and pattern detector circuit may be further operable to generate an automatic gain control signal as a function of the high frequency phase error, the automatic gain control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal.

Abstract: A predistorter is disclosed that predistorts an input signal based on one or more static coefficients that are representative of a non-linear distortion characteristic of an amplifier. The input signal is also processed based on a non-linear gain parameter that reduces an error metric between the input signal and a feedback signal. The nonlinear gain parameter adapts an amount of nonlinearity introduced by the predistorter. The non-linear gain adaptation is performed, for example, when the input voltage is above a threshold input voltage. The input signal can be processed by multiplying the input signal by the non-linear gain parameter followed by table-coefficient processing, or by both multiplying the input by the non-linear gain parameter followed by dividing the table-coefficient processed output signal by the same non-linear gain parameter. The input signal can also be processed based on a feedback gain parameter that compensates for a small-signal gain of the feedback loop. The feedback gain parameter attempts to maintain a small-signal gain of approximately unity.

Abstract: A method is presented in this paper for the design of high speed CMOS operational amplifiers (op-amp). The op-amp consists of an operational transconductance amplifier (OTA) followed by an output buffer. The OTA is compensated with a capacitor connected between the input and output of the buffer. An op-amp is designed in a 0.18 /spl mu/m standard digital CMOS technology and exhibits 86 dB DC gain. The unity gain frequency and phase margin are 392 MHz and 73/spl deg/, respectively, for a parallel combination of 2 pF and 1 k/spl Omega/ load. As compared to the conventional approach, the proposed compensation method results in a 1.5 times increase in unity gain frequency and a 35/spl deg/ improvement in the phase margin under the same load conditions.

Abstract: This paper discusses a tolerance design approach for the feedback compensation networks of DC/DC switching regulators, identifying the most reliable solutions among different feasible alternatives that fulfil closed-loop design constraints. A voltage-mode-regulated DC/DC buck converter is considered as a case study. Given the performance and stability constraints, as tolerance ranges for crossover frequency and phase margin, feasible design solutions are sought by means of Monte Carlo and interval arithmetic computations. The search space is a set of available commercial values of RC parameters and related tolerances. Best design is identified by a weighted fitness function, exploring the set of solutions provided by different design approaches. The results presented in the paper highlight that the tolerance design approach allows one to find compensation networks that fit the given performance/robustness priorities better than those ones found by means of the classical nominal design approach.

Abstract: We propose a self-tuning proportional-integral (PI) controller for active queue management (AQM) in the Internet. Classical control theory is applied in the controller design. We assign a proper interval of gain and phase margins to achieve good AQM performance while adapting the AQM control system to great traffic load changes very well. Based on the knowledge of the queue size, our PI controller can regulate the TCP source window size to clamp the steady value of queue size to specified target buffer occupancy. OPNET simulations demonstrate that, with our self-tuning PI controller applied, the network shows good stability robustness.

Abstract: A system (650, 690) for controlling gain in a polar loop (550) is disclosed. Embodiments of the invention provide for a substantially constant gain tolerant of changes in supply voltage, ambient temperature, and/or manufacturing process.

Abstract: In order to rapidly control the gains of a plurality of variable gain amplifiers VGAs, each of gain control circuits is configured to determine a gain to be set therein, based on gain control information received from other gain control circuits existing in its preceding stage or stages and the signal level detected by a level detector circuit connected thereto. By carrying out such gain control, a total application gain is stabilized more quickly by gain control. Therefore, even in receiving systems that the preparation period for reception is very short, desired gain control is achieved within this period and stable data reception can be performed.

Abstract: A method and apparatus to dynamically modify internal compensation of a low dropout (LDO) voltage regulator is provided. The LDO voltage regulator includes an output pass transistor, an error amplifier, a bias transistor and a compensation network. The compensation network is connected between a gate and a drain of the output pass transistor to compensate for the feedback loop. The compensation network and the bias transistor generate pole-zero pairs to perform a maximum 45 degrees phase shift before reaching the crossover frequency in the LDO voltage regulator. Therefore a minimum 45 degrees phase margin is provided for the feedback loop in various load conditions. Furthermore, the pole-zero pairs produced in the LDO voltage regulator are adaptively adjusted according to load conditions, so that the bandwidth is optimized and faster transient response is achieved.

Abstract: In this paper, we present modifications to the constant-gm bias circuit and the Miller-lead compensation technique which eliminate or minimize some of their shortcomings. First, we demonstrate how parasitic pad capacitance can cause instability in the constant-gm bias circuit, and show that the transconductance is constant only for specific bias conditions. Next, we suggest a new circuit topology that requires 75% less compensation capacitance to achieve stability. We also discuss problems with Miller-lead compensation that arise from temperature, process and load variations. Finally, we present a new biasing technique to correct these problems, and, through simulation, demonstrate a 40/spl deg/ improvement in phase margin over load current variations.

Abstract: An iterative controller tuning method based on a frequency criterion is proposed in this paper. The frequency criterion is defined as the weighted sum of squared errors between the desired and actual value of the modulus margin (inverse of the infinity norm of the sensitivity function), phase margin and crossover frequency. The criterion is minimized using the iterative Gauss-Newton algorithm. The gradient and Hessian of the criterion can be expressed in terms of the derivatives of the open-loop system with respect to the frequency. These derivatives, as well as the robustness margins and the related frequencies are computed using a plant model. Simulation examples illustrate the effectiveness and the simplicity of the proposed method for controller tuning.

Abstract: An amplifier having an active and passive gain stage connect to a load for driving a load according to a system analog input. A first embodiment of the amplifier in accordance with the present invention includes a logic network connected between a comparator network and a switching system, wherein the comparator network connects to the passive gain stage. Specifically, the active gain stage may include an active filter connected to receive an analog or digital input and provide a difference between the analog or digital input and the feedback signal relative to the gain factor of a gain unit connected to the active filter. The passive gain stage includes a passive filter. The logic network generates at least one switching signal which controls the switching system that includes at least one switching device to selectively provide power to the load. An output signal from the switching system provides output for the amplifier and is fed back to the active gain stage. In another embodiment, the output is a two-level signal and the passive and active filters are second order low pass filters, where the gain factor is about 25 or more. In yet another embodiment, the gain factor is approximately 250. Moreover, the amplifier may include a digital delta-sigma modulator connected to supply a two level input.

Abstract: A fully differential operational amplifier (op-amp) is described that simultaneously achieves low power consumption and wide bandwidth by employing current-reusing feedforward compensation scheme. In contrast to the conventional feedfoward frequency compensation, the newly developed scheme re-uses the bias current of the second stage of op-amp and therefore the power consumption is minimized. The op-amp designed in a 0.25/spl mu/m CMOS technology achieves 77dB DC gain, 870MHz unity gain frequency and 56/spl deg/ phase margin for 1pF load capacitance. The op-amp draws 1.8mA from a 2.5V supply.

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract: Fast tool servo is one of the key components in manufacturing complex surfaces with nanometer-scale resolution. This paper presents the controller design for an electromagnetically driven fast tool servo. First, the nonlinear and frequency-dependent actuator is linearized with dynamic nonlinear compensation method. Next, the plant is compensated with lead-lag controller plus integrator to achieve the cross over frequency at one twentieth of the sampling frequency. Finally, repetitive controller is plugged into the compensated loop of the last step to improve the tracking of spindle synchronized trajectory and the rejection of spindle rotation induced disturbance. Based on the integrator gain of the compensated loop, a method of tuning repetitive controller gains is presented to ensure the closed loop system phase margin in spite of changes of repetitive controller poles. Experiment is conducted on a diamond turning machine. For 100 kHz sampling frequency, the achieved closed loop bandwidth is 10 kHz with -3 dB attenuation. The maximum stroke is 50 /spl mu/m for up to 1 kHz operation and the maximum acceleration is 160 g up to 3 kHz. An aluminum part is turned with sinusoidal surface to demonstrate the usability of the control.

Abstract: A high frequency variable gain amplification device 100 includes: a feedback circuit 103 capable of changing a feedback impedance to adjust the gain of an amplifier 101 in accordance with a control signal from a control device 200; and a current consumption adjustment circuit 102 capable of adjusting current consumption of the amplifier 101. The control device 200 controls the feedback impedance and the current consumption based on a desired signal power level and an undesired signal power level. If the desired signal power level exceeds a predetermined value, the control device 200 reduces the feedback impedance to increase the amount of a feedback signal, thereby allowing the amplifier 101 to operate with low gain so as to prevent the distortion characteristic from being reduced and to reduce the current consumption.

Abstract: A quasi-linear feedback compensator is one in which its poles depend in an appropriate way on its gain. The reason for introducing this new concept was the desire to remove the limitation to performance imposed by a plant with more than one pole in excess of its zeros. In this article it is shown that this objective is realized for plants with zeros in the left half of the complex plane. The consequences are surprising. In time domain it is possible to track arbitrarily fast a class of reference inputs despite a large class of disturbances and uncertainty in plant parameters. The response is non-oscillatory for high enough compensator gains, which is explained by the automatic adaptation of the closed loop poles to stability and stability margins for such gains. And in frequency domain the phase margin tends to 90° while the gain margin and crossover frequency become unlimited. Technically the design procedure of quasi-linear compensators presented here is based on our theoretical result concerning the as...

Abstract: Some performance results of the Cartesian feedback and feedforward linearization techniques applied to a class-A power amplifier operating at 28 GHz are presented. The performance of the combination of HMMC-5040 (driver) and HMMC-5033 (power amplifier) is used as benchmark for simulation analysis. This analysis is addressed to show the key aspects on spectral regrowth due to phase margin and loop gain for Cartesian feedback, and time delay, phase and gain mismatch for feedforward. A 16 QAM digital signal at 10 Mbits/s filtered with a squared raised cosine filter with /spl alpha/=0, 25 is used as test signal.

Abstract: In this paper, a method is presented to estimate the amount of over/undershoot and the settling time of the voltage response of a DC-DC converter due to load transients. The method uses the phase margin and crossover frequency of the voltage loop frequency response and the amount of load current change DI to estimate the peak voltage deviation during a load transient. The phase margin and loop crossover frequency is calculated using a unique macro model of the converter which is based on measurement, rather than the usual linearized analytical model and is accurate within a few percentage points for both the phase margin and crossover frequency. The method uses the fact that the behavior of converter+load can be approximated by a second order RLC circuit and maps the dynamics of the latter to estimate the dynamic response of the converter+load system. The predicted and measured response of a 40 A, 1.2 V DC-DC converter is presented to show the close agreement between estimated and measured voltage deviation. The method can be used for determining the amount of capacitance that should be added to satisfy the output voltage undershoot/overshoot requirements during transients and hence be used to test what-if scenarios before committing to hardware.

Abstract: Nowadays, piezoelectric transformers (PT) are a good alternative to substitute magnetic materials in AC/DC and DC/DC converters. They have high isolation voltage and operate at high frequencies, with lower losses. However, their optimum operating frequency exhibits a strong dependence on different parameters, such as temperature, load or voltage level applied. This usually causes an inconvenience, because this drift affects PT gain and efficiency, which can vary enormously within a few hundred of hertzs. On the other hand, it is not only necessary to ensure the PT is driven at the proper frequency -in terms of gain and efficiency, including zero voltage switching (ZVS) in the power stage- but also to regulate the output voltage. In this paper, two simple feedback loops are implemented in a PT based DC/DC converter: One of them adjusts the switching frequency to obtain the best gain and efficiency. The other performs the output voltage regulation.

Abstract: A fast lock phase lock loop (PLL) with minimal phase disturbance when switching from wide bandwidth mode to narrow bandwidth mode including a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator, and a sequencer circuit for, at a first time, initiating an increase in the charge pump current to increase the loop gain to widen the loop bandwidth and initiating a decrease in the resistance in the loop filter to increase the phase margin of the PLL in the wide bandwidth mode; at a second time, initiating a reduction in the charge pump current to reduce the loop gain and bandwidth, and; at a third time, initiating an increase in the resistance in the loop filter to increase the phase margin of the PLL in the narrow bandwidth mode.

Abstract: A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.

Abstract: An evolutionary approach to worst case tolerance design is introduced here, with a focus on feedback compensation networks for dc-dc switching converters. Assumed that varying parameters values are uniformly distributed and uncorrelated, as provided by the worst case approach, the proposed algorithm, of general applicability, seeks for the set of nominal values and tolerances of the circuit parameters ensuring that the design constraints are met and that a user-defined circuit performance index assumes its optimal value. Design constraints, are fixed in the frequency domain, in terms of acceptability ranges of loop gain crossover frequency and phase margin, to guarantee closed loop stability and the desired dynamic performance. Resistive and capacitive compensation network's parameters values are chosen within a suitable database of couples nominal value/tolerance available on the market, while the nominal values and tolerances of the parameters of the power stage are fixed. Referring to a buck dc-dc switching regulator, two widely used different compensation network topologies are compared in terms of reliability, robustness, and cost of components. Simulation results show the wide usefulness of the proposed method in supporting designer decisions.

Abstract: PROBLEM TO BE SOLVED: To provide a calculation method of a control parameter that calculates at high speed the control parameter of a motor control device stable and smooth in response and high in control responsiveness, and the motor control device that uses the control parameter calculation method. SOLUTION: The calculation method calculates the control parameter of the motor control device that comprises a speed control means that generates a first torque command so that a speed command and the detected speed of a motor coincides with each other, and a torque control means that drives the motor according to the first torque command or a second torque command that is the result of the filter processing of the first torque command. A load frequency characteristic that is a frequency characteristic between the first or the second torque command and a motor speed is obtained (S1), the maximum value of a gain in a frequency range wherein a phase of the load frequency characteristic is -180+α[deg] is obtained by using a prescribed phase margin α (S2), and the control parameter (speed response frequency) of the speed control means is calculated on the basis of the maximum value of the gain (S3). COPYRIGHT: (C)2005,JPO&NCIPI