Abstract: An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.

Abstract: The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

Abstract: A full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-/spl mu/m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mV/sub pp/. The filter active area is only 900 /spl times/ 200 /spl mu/m/sup 2/. The supply voltages used are /spl plusmn/1.5 V.

Abstract: The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

Abstract: A new method for PID controller tuning based on Bode's integrals is proposed. It is shown that the derivatives of amplitude and phase of a plant model with respect to frequency can be approximated by Bode's integrals without any model of the plant. This information can be used to design a PID controller for slope adjustment of the Nyquist diagram and improve the closed-loop performance. Besides, the derivatives can be also employed to estimate the gradient and the Hessian of a frequency criterion in an iterative PID controller tuning method. The frequency criterion is defined as the sum of squared errors between the desired and measured gain margin, phase margin and crossover frequency. The method benefits from specific feedback relay tests to determine the gain margin, the phase margin and the crossover frequency of the closed-loop system. Simulation examples and experimental results illustrate the effectiveness and the simplicity of the proposed method to design and tune the PID controllers.

Abstract: A switching signal generator for a switching power supply employing a DC-DC modulator has an adder, an integrator and a quantizer. A gate driver circuit is provided upstream of a power switch element and receives a quantizer output. By feeding back a gate driver circuit output to the adder of the ΔΣ-modulator, a large phase margin is obtained at a high-frequency switching. The switching signal generator for the ΔΣ-modulation type switching power supply has an improved direct-current transmission linearity characteristic relative to direct-current input, and that is stably controllable and of high efficiency. Furthermore, a DC-DC converter has an adder, an integrator and a quantizer, the integrator having a mechanism for adjusting its gain. The gain-adjusting mechanism receives a signal from a current flowing internally of the DC-DC converter, a voltage internally of the converter, or a converter output voltage to control gain of the integrator so that the amplitude of output voltage of the integrator is not saturated and a comparator is capable of high-speed operation, a ΔΣ-modulation type DC-DC converter is provided that is unlikely to undergo oscillation especially at a high sampling frequency, and that produces a stable output voltage.

Abstract: System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115 ) and an integral loop gain block (integral loop gain block 1120 ). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

Abstract: This paper presents a control design method for determining proportional-integral-type controllers satisfying specifications on gain margin, phase margin, and an upper bound on the (complementary) sensitivity for a finite set of plants. The approach can be applied to plants that are stable or unstable, plants given by a model or measured data, and plants of any order, including plants with delays. The algorithm is efficient and fast, and as such can be used in near real-time to determine controller parameters (for online modification of the plant model including its uncertainty and/or the specifications). The method gives an optimal controller for a practical definition of optimality. Furthermore, it enables the graphical portrayal of design tradeoffs in a single plot, highlighting the effects of the gain margin, complementary sensitivity bound, low frequency sensitivity and high frequency sensor noise amplification.

Abstract: This invention provides a stable power supply apparatus enabling the high speed response. Hitherto, it was necessary to secure both of the gain margin and the phase margin on the Bode diagram of the loop transfer function when the PID feedback control was carried out in the power supply apparatus. The form of the transfer function of the controller in the power supply apparatus of this invention is the same, but a set of coefficient values in the transfer function is completely different, and the controller secures only the phase margin without securing the gain margin. Furthermore, the transfer function of the controller indicates a part with an extreme decrease in the gain and a trap point in which the phase is sharply delayed on the Bode diagram. This is achieved by applying the integral element of the PID to a frequency range that is higher than the resonance frequency of the LC filter. As a result, the high speed response becomes possible without losing the stability. Moreover, there is no case in which difficulty as to the setting of the circuit constants rises.

Abstract: Systems and techniques for gain control include amplifying a signal with an amplifier having a gain represented by one of a plurality of gain curves depending on a value of a parameter, the signal being amplified at a first one of the parameter values, and controlling the gain of the amplified signal from a predetermined gain curve relating to the gain curve of the amplifier for a second one of the parameter values by adjusting a gain control signal corresponding to a point on the predetermined gain curve as a function of the first one of the parameter values, and applying the adjusted gain control signal to the amplifier. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching or loop tilter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer- N PLL's): a signal-tonoise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

Abstract: An improved frequency compensation technique is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor to form a composite gain-enhanced feedforward stage in a two-stage amplifier so as to broaden the gain bandwidth via low-frequency pole-zero cancellation at heavy capacitive loads, but yet without increasing substantial power consumption. The technique has been confirmed by the experimental results. An operational amplifier has been designed to drive a capacitive load of 300 pF. The amplifier exhibits a dc gain of 87 dB, a gain bandwidth of 10.4 MHz at 63.7/spl deg/ phase margin, an average slew rate of 3.5 V//spl mu/s, a compensation capacitor of only 6 pF while consuming 2.45 mW at a 3-V supply in a standard 0.6-/spl mu/m CMOS technology.

Abstract: Method and system are disclosed for automated calibration of the VCO gain in phase modulators. The method and system of the invention comprises synthesizing, in a phase modulator, a signal having a given output frequency using a controlled oscillator having a frequency control input, a modulation input, and a feedback loop. A frequency control signal is applied to the frequency control input, and gain variation of the controlled oscillator is compensated for outside of the feedback loop via the modulation input. The method and system of the invention may be employed in any telecommunication system that uses phase and amplitude modulation, including EDGE and WCDMA systems.

Abstract: In this paper, an iterative procedure for achieving gain and phase margin specifications for a PI controller is presented. The iteration scheme is based on the use of two relay tests applied to the closed-loop system. The first relay test is standard, and it is used here to obtain the gain margin of the closed-loop system at each iteration step. The second one is applied to the closed-loop system such that a limit cycle is developed at the loop gain crossover frequency. Under this condition, it is possible to obtain an estimate of the phase margin of the loop transfer function. The procedure is used for PI controller tuning in a vanadium-dioxide (VO/sub 2/) thin-film characterization experiment, with desired gain and phase margin specifications.

Abstract: This paper introduces a new fuzzy logic controller (FLC) using inductor current feedback for significantly improving the dynamic performance of DC-to-DC converters. Inductor current plays an important role in high performance DC-to-DC converter control and FLC is suitable to deal with time-varying nonlinear nature of power converters. Based on the feedback of the inductor current, the new control method combines the merits of both the conventional FLC and current mode control. The dynamic performance of power converter system is improved. Furthermore, in order to enhance system robustness and adaptability, a new nonlinear configuration called extended state observer (ESO) is developed. By using ESO, the influence of load disturbances and parameter changes are precisely estimated and compensated without accurate knowledge of converter parameters. Simulation results have demonstrated that the proposed methods ensure good robustness and adaptability under modeling uncertainty and external disturbance, such as load current variation, supply voltage changes and converter parameter changes. It is concluded that the proposed topology produces substantial improvement of dynamic performances such as small overshoot, more damping and fast transient time under different operating conditions. In addition, small signal frequency response analysis demonstrates that by using the proposed FLC, the bandwidth and phase margin of the closed loop system have been significantly increased.

Abstract: Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

Abstract: In this paper, for the first time, the fractional order disturbance observer (FO-DOB) is proposed for vibration suppression applications such as hard disk drive servo control. It has been discovered in a recently published US patent application (US20010036026) (Chen et al., 2001) that there is a tradeoff between the the phase margin loss and the strength of the low frequency vibration suppression. Given the required cutoff frequency of the low pass filter, also known as the Q-filter, it turns out that the relative degree of the Q-filter is the major tuning knob for this tradeoff. As a motivation for the fractional order Q-filter, a solution based on integer order Q-filter with a variable relative degree is introduced which is the key contribution of US20010036026. Then, a fractional order disturbance observer based on the fractional order Q-filter is proposed. The implementation issue is also discussed. The nice point of this paper is that the traditional DOB is extended to fractional order DOB with the advantage that the FO-DOB design is now no longer conservative or aggressive, i.e., given the cutoff frequency and the desired phase margin, we can uniquely determine the fractional order of the low pass filter.

Abstract: A controller for a multiphase converter including an error amplifier, a gain resistor, a current sense circuit and a gain adjust amplifier. The error amplifier generates an error signal based on an error voltage developed across a feedback resistance. The current sense circuit converts each of multiple sensed load currents into corresponding proportional voltages. The gain adjust amplifier circuit receives the proportional voltages and operates to apply at least one gain adjust voltage to the gain resistor to develop a gain adjust current that is applied through the feedback resistance to adjust gain. In one embodiment, the proportional voltages are time multiplexed or averaged to provide the gain adjust voltage(s). An IC integrating the multiphase converter need only include a single gain pin for coupling to a gain resistor to set gain for each phase.

Abstract: A new architecture for constant-g/sub m/, rail-to-rail(R-R) input stages is presented that has less than 5% deviation in g/sub m/ over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. Employing these techniques a low-power operational transconductance amplifier (OTA) with 100 MHz unity-gain bandwidth, 106 dB gain, 60/spl deg/ phase margin, 2.65 V swing, and 6.4 nV//spl radic/Hz input-referred noise with R-R input common-mode range is realized in a 0.8 /spl mu/m CMOS technology. This amplifier dissipates 10 mW from a 3V power supply.

Abstract: A single stage switched capacitor programmable gain amplifier uses programmable capacitor values to adjust gain factors. The operation of the amplifier is described by a transfer function having two gain factors: (C 1 /C 2 ) and (C 2 /C 3 ). The gain factor of C 1 /C 2 applies during the holding phase and the gain factor of C 2 /C 3 applies during the sampling phase. The transfer function is equal to the product of the two gain factors: (C 1 /C 2 )×(C 2 /C 3 ) such that the transfer function is equal to (C 1 /C 3 ). The intermediate element C2 can be adjusted to maximize bandwidth because C 2 is independent of the total transfer gain. Accordingly, the intermediate element C 2 is substantially fixed from the holding phase to the following sampling phase such that the bandwidth of the programmable gain amplifier is maximized in the two phases.

Abstract: This paper presents a control design algorithm for determining PI-type controllers satisfying specifications on gain margin, phase margin, and an upper bound on the (complementary) sensitivity for a finite set of plants. Important properties of the algorithm are: (i) it can be applied to plants of any order including plants with delay, unstable plants, and plants given by measured data, (ii) it is efficient and fast, and as such can be used in near real-time to determine controller parameters (for on-line modification of the plant model including its uncertainty and/or the specifications), (iii) it can be used to identify the optimal controller for a practical definition of optimality, and (iv) it enables graphical portrayal of design tradeoffs in a single plot (highlighting tradeoffs among the gain margin, complementary sensitivity bound, low frequency sensitivity and high frequency sensor noise amplification).

Abstract: A phase locked loop frequency synthesizer in which frequency gain of a voltage controlled oscillator is compensated is disclosed. The phase locked loop frequency synthesizer measures a frequency gain variation of the voltage controlled oscillator and compensates the variation by controlling phase gain of a phase comparator or voltage gain of a loop filter. Gain characteristics of the voltage controlled oscillator are detected and fed back to control frequency gain of the voltage controlled oscillator, so as to allow the voltage controlled oscillator to have uniform frequency gain. Accordingly, the phase locked loop frequency synthesizer can obtain uniform loop gain irrespective of a frequency gain variation of the voltage controlled oscillator and provide optimum phase noise characteristics and stability.

Abstract: A gain control system in a Direct Conversion Receiver or similar receiver, includes an automatic gain control circuit which determines whether a low noise amplifier, which amplifies signals from an antenna prior to mixing with signals from a local oscillator, should be set to a high gain or a low gain. The output of the mixer is analyzed by a blocker detect circuit to determine whether a blocker signal is present. Based on the presence of a blocker signal and the power level of the useful signal, the gain of the low noise amplifier may be reduced from the high gain to an intermediate gain in order to reduce self mixing between the radio frequency and local oscillator ports of the mixer, which may lead to dynamic DC offsets.

Abstract: A variable gain control amplifier ( 10 ) and method provides a substantially constant input impedance and output impedance, and provides a substantially constant noise figure and third order harmonic. The variable gain control amplifier ( 10 ) includes an amplifier stage including at least a first intermediate fixed gain stage ( 22 ) operative to produce a first intermediate signal ( 30 ) in response to the input signal ( 20 ). The variable gain control amplifier ( 10 ) further includes at least a second intermediate fixed gain stage ( 24 ) operative to produce an output signal ( 18 ) in response to the first intermediate signal ( 30 ). A feedback circuit ( 16 ) is operative to produce a gain control signal ( 32 ) in response to the output signal ( 18 ). A gain control circuit ( 26 ) is coupled to the at least first intermediate fixed gain stage ( 22 ) and the second intermediate fixed gain stage ( 24 ), and receives the gain control signal ( 32 ) to control an amplitude of the intermediate signal ( 30 ).

Abstract: An iterative controller auto-tuning method based on a frequency criterion is proposed. The frequency criterion is defined as the weighted sum of squared errors between the desired and measured gain margin, phase margin and crossover frequency. A relay feedback test is used to automatically obtain a non-parametric model of the open-loop system in a very important region for control design. The gain and phase margins as well as the crossover frequency are estimated with the non-parametric model using interpolations. The gradient and Hessian of the frequency criterion can be expressed in terms of the derivatives of the open-loop system with respect to the frequency. These derivatives can also be estimated with a good accuracy thanks to the non-parametric model. Since no assumptions are made on the plant, the method is valid for a very wide class of linear systems. Simulation examples illustrate the effectiveness and simplicity of the proposed method.

Abstract: A programmable gain amplifier with three stages uses fine steps, has a large gain range, and is monotonic. The first stage comprises several amplifiers, each including a resistive feedback loop. The feedback loop comprises a series of resistors, with each resistor acting as a tap. Since the number of resistors in the loop is unchanging, monotonicity and stability is guaranteed when resistance is increased using successive taps. A switch system connects two taps at a time to an interpolation stage. Each of these taps corresponds to a specific resistor level, and thus a gain level. The interpolation stage uses a plurality of current sources inside a feedback amplifier to control the interpolation, in order to provide fine gain steps.

Abstract: In this paper, we present a new opamp based on dynamic threshold voltage (DTMOS) transistors for low voltage applications (1 V). The opamp is a two stage configuration, with differential input pairs followed by a single ended class AB output. The input stage uses DTMOS devices for input common-mode range enhancement. The performed simulation shows a dc open loop gain of 64.4 dB, a phase margin of 64/spl deg/ and unity gain frequency of 35.7 MHz under a 10 k/spl Omega/ and 5 pF load, using the 0.18 /spl mu/m CMOS technology. The opamp has a CMRR of 84 dB, input and output swings of 0.7 V and 0.9 V respectively.

Abstract: An operational amplifier circuit that provides negative feedback and high gain is described. Specifically, the circuit comprises a first gain stage, a second gain stage, a feedback circuit, and a biasing circuit.